//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/Streams.h"
#include <set>
+#include <algorithm>
using namespace llvm;
// runEnums - Print out enum values for all of the registers.
const std::string &TargetName = Target.getName();
std::string ClassName = TargetName + "GenRegisterInfo";
- OS << "#include \"llvm/Target/MRegisterInfo.h\"\n";
+ OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
OS << "#include <string>\n\n";
OS << "namespace llvm {\n\n";
- OS << "struct " << ClassName << " : public MRegisterInfo {\n"
- << " " << ClassName
+ OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
+ << " explicit " << ClassName
<< "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
- << " int getDwarfRegNum(unsigned RegNum) const;\n"
+ << " virtual int getDwarfRegNumFull(unsigned RegNum, "
+ << "unsigned Flavour) const;\n"
+ << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
<< " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
<< "};\n\n";
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
if (i) OS << ",\n";
OS << " " << RegisterClasses[i].getName() << "RegClassID";
- if (!i) OS << " = 1";
+ OS << " = " << (i+1);
}
OS << "\n };\n\n";
static void addSuperReg(Record *R, Record *S,
std::map<Record*, std::set<Record*> > &SubRegs,
std::map<Record*, std::set<Record*> > &SuperRegs,
- std::map<Record*, std::set<Record*> > &Aliases,
- RegisterInfoEmitter &RIE) {
+ std::map<Record*, std::set<Record*> > &Aliases) {
if (R == S) {
cerr << "Error: recursive sub-register relationship between"
- << " register " << RIE.getQualifiedName(R)
+ << " register " << getQualifiedName(R)
<< " and its sub-registers?\n";
abort();
}
if (SuperRegs.count(S))
for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
E = SuperRegs[S].end(); I != E; ++I)
- addSuperReg(R, *I, SubRegs, SuperRegs, Aliases, RIE);
+ addSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
}
static void addSubSuperReg(Record *R, Record *S,
std::map<Record*, std::set<Record*> > &SubRegs,
std::map<Record*, std::set<Record*> > &SuperRegs,
- std::map<Record*, std::set<Record*> > &Aliases,
- RegisterInfoEmitter &RIE) {
+ std::map<Record*, std::set<Record*> > &Aliases) {
if (R == S) {
cerr << "Error: recursive sub-register relationship between"
- << " register " << RIE.getQualifiedName(R)
+ << " register " << getQualifiedName(R)
<< " and its sub-registers?\n";
abort();
}
if (!SubRegs[R].insert(S).second)
return;
- addSuperReg(S, R, SubRegs, SuperRegs, Aliases, RIE);
+ addSuperReg(S, R, SubRegs, SuperRegs, Aliases);
Aliases[R].insert(S);
Aliases[S].insert(R);
if (SubRegs.count(S))
for (std::set<Record*>::iterator I = SubRegs[S].begin(),
E = SubRegs[S].end(); I != E; ++I)
- addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases, RIE);
+ addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
}
+class RegisterSorter {
+private:
+ std::map<Record*, std::set<Record*> > &RegisterSubRegs;
+
+public:
+ RegisterSorter(std::map<Record*, std::set<Record*> > &RS)
+ : RegisterSubRegs(RS) {};
+
+ bool operator()(Record *RegA, Record *RegB) {
+ // B is sub-register of A.
+ return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB);
+ }
+};
+
// RegisterInfoEmitter::run - Main register file description emitter.
//
void RegisterInfoEmitter::run(std::ostream &OS) {
// Emit the register list now.
OS << " // " << Name
<< " Register Class Value Types...\n"
- << " static const MVT::ValueType " << Name
+ << " static const MVT " << Name
<< "[] = {\n ";
for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
OS << getEnumName(RC.VTs[i]) << ", ";
<< RC.getName() + "SubRegClasses" << ", "
<< RC.getName() + "SuperRegClasses" << ", "
<< RC.SpillSize/8 << ", "
- << RC.SpillAlignment/8 << ", " << RC.getName() << ", "
- << RC.getName() << " + " << RC.Elements.size() << ") {}\n";
+ << RC.SpillAlignment/8 << ", "
+ << RC.CopyCost << ", "
+ << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size()
+ << ") {}\n";
}
OS << "}\n";
std::map<Record*, std::set<Record*> > RegisterSuperRegs;
std::map<Record*, std::set<Record*> > RegisterAliases;
std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors;
+ std::map<Record*, std::vector<int> > DwarfRegNums;
+
const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
<< " multiple times!\n";
RegisterImmSubRegs[R].insert(SubReg);
addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
- RegisterAliases, *this);
+ RegisterAliases);
}
}
for (std::map<Record*, std::set<Record*> >::iterator
I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
+ std::vector<Record*> SubRegsVector;
for (std::set<Record*>::iterator ASI = I->second.begin(),
E = I->second.end(); ASI != E; ++ASI)
- OS << getQualifiedName(*ASI) << ", ";
+ SubRegsVector.push_back(*ASI);
+ RegisterSorter RS(RegisterSubRegs);
+ std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS);
+ for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i)
+ OS << getQualifiedName(SubRegsVector[i]) << ", ";
OS << "0 };\n";
}
for (std::map<Record*, std::set<Record*> >::iterator
I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
+
+ std::vector<Record*> SuperRegsVector;
for (std::set<Record*>::iterator ASI = I->second.begin(),
E = I->second.end(); ASI != E; ++ASI)
- OS << getQualifiedName(*ASI) << ", ";
+ SuperRegsVector.push_back(*ASI);
+ RegisterSorter RS(RegisterSubRegs);
+ std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS);
+ for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i)
+ OS << getQualifiedName(SuperRegsVector[i]) << ", ";
OS << "0 };\n";
}
OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
- OS << " { \"NOREG\",\t0,\t0,\t0,\t0 },\n";
+ OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0,\t0 },\n";
// Now that register alias and sub-registers sets have been emitted, emit the
// register descriptors now.
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
const CodeGenRegister &Reg = Registers[i];
OS << " { \"";
- if (!Reg.TheDef->getValueAsString("Name").empty())
- OS << Reg.TheDef->getValueAsString("Name");
+ if (!Reg.TheDef->getValueAsString("AsmName").empty())
+ OS << Reg.TheDef->getValueAsString("AsmName");
else
OS << Reg.getName();
+ OS << "\",\t\"";
+ if (!Reg.TheDef->getValueAsString("Name").empty()) {
+ OS << Reg.TheDef->getValueAsString("Name");
+ } else {
+ // Default to "name".
+ if (!Reg.TheDef->getValueAsString("AsmName").empty())
+ OS << Reg.TheDef->getValueAsString("AsmName");
+ else
+ OS << Reg.getName();
+ }
OS << "\",\t";
if (RegisterAliases.count(Reg.TheDef))
OS << Reg.getName() << "_AliasSet,\t";
// Emit the constructor of the class...
OS << ClassName << "::" << ClassName
<< "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
- << " : MRegisterInfo(RegisterDescriptors, " << Registers.size()+1
+ << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
<< " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n";
- // Emit information about the dwarf register numbers.
- OS << "int " << ClassName << "::getDwarfRegNum(unsigned RegNum) const {\n";
- OS << " static const int DwarfRegNums[] = { -1, // NoRegister";
+ // Collect all information about dwarf register numbers
+
+ // First, just pull all provided information to the map
+ unsigned maxLength = 0;
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
- if (!(i % 16)) OS << "\n ";
- const CodeGenRegister &Reg = Registers[i];
- int DwarfRegNum = Reg.TheDef->getValueAsInt("DwarfNumber");
- OS << DwarfRegNum;
- if ((i + 1) != e) OS << ", ";
+ Record *Reg = Registers[i].TheDef;
+ std::vector<int> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
+ maxLength = std::max((size_t)maxLength, RegNums.size());
+ if (DwarfRegNums.count(Reg))
+ cerr << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
+ << "specified multiple times\n";
+ DwarfRegNums[Reg] = RegNums;
}
- OS << "\n };\n";
- OS << " assert(RegNum < (sizeof(DwarfRegNums)/sizeof(int)) &&\n";
- OS << " \"RegNum exceeds number of registers\");\n";
- OS << " return DwarfRegNums[RegNum];\n";
- OS << "}\n\n";
+
+ // Now we know maximal length of number list. Append -1's, where needed
+ for (std::map<Record*, std::vector<int> >::iterator
+ I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
+ for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
+ I->second.push_back(-1);
+
+ // Emit information about the dwarf register numbers.
+ OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
+ << "unsigned Flavour) const {\n"
+ << " switch (Flavour) {\n"
+ << " default:\n"
+ << " assert(0 && \"Unknown DWARF flavour\");\n"
+ << " return -1;\n";
+
+ for (unsigned i = 0, e = maxLength; i != e; ++i) {
+ OS << " case " << i << ":\n"
+ << " switch (RegNum) {\n"
+ << " default:\n"
+ << " assert(0 && \"Invalid RegNum\");\n"
+ << " return -1;\n";
+
+ for (std::map<Record*, std::vector<int> >::iterator
+ I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
+ int RegNo = I->second[i];
+ if (RegNo != -2)
+ OS << " case " << getQualifiedName(I->first) << ":\n"
+ << " return " << RegNo << ";\n";
+ else
+ OS << " case " << getQualifiedName(I->first) << ":\n"
+ << " assert(0 && \"Invalid register for this mode\");\n"
+ << " return -1;\n";
+ }
+ OS << " };\n";
+ }
+
+ OS << " };\n}\n\n";
OS << "} // End llvm namespace \n";
}
projects / oota-llvm.git / blobdiff