// runEnums - Print out enum values for all of the registers.
void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
- CodeGenTarget Target;
+ CodeGenTarget Target(Records);
const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
OS << "enum {\n NoRegister,\n";
for (unsigned i = 0, e = Registers.size(); i != e; ++i)
- OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
+ OS << " " << Registers[i].getName() << " = " <<
+ Registers[i].EnumValue << ",\n";
+ assert(Registers.size() == Registers[Registers.size()-1].EnumValue &&
+ "Register enum value mismatch!");
OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
OS << "};\n";
if (!Namespace.empty())
void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
EmitSourceFileHeader("Register Information Header Fragment", OS);
- CodeGenTarget Target;
+ CodeGenTarget Target(Records);
const std::string &TargetName = Target.getName();
std::string ClassName = TargetName + "GenRegisterInfo";
<< " { return false; }\n"
<< " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
<< " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
+ << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
<< "};\n\n";
const std::vector<CodeGenRegisterClass> &RegisterClasses =
if (!RegisterClasses.empty()) {
OS << "namespace " << RegisterClasses[0].Namespace
<< " { // Register classes\n";
-
+
OS << " enum {\n";
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
if (i) OS << ",\n";
OS << " " << RegisterClasses[i].getName() << "RegClassID";
- OS << " = " << (i+1);
+ OS << " = " << i;
}
OS << "\n };\n\n";
OS << "} // End llvm namespace \n";
}
-bool isSubRegisterClass(const CodeGenRegisterClass &RC,
- std::set<Record*> &RegSet) {
- for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
- Record *Reg = RC.Elements[i];
- if (!RegSet.count(Reg))
- return false;
- }
- return true;
-}
-
static void addSuperReg(Record *R, Record *S,
std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
}
-// Map SubRegIndex -> Register
-typedef std::map<Record*, Record*, LessRecord> SubRegMap;
-// Map Register -> SubRegMap
-typedef std::map<Record*, SubRegMap> AllSubRegMap;
+struct RegisterMaps {
+ // Map SubRegIndex -> Register
+ typedef std::map<Record*, Record*, LessRecord> SubRegMap;
+ // Map Register -> SubRegMap
+ typedef std::map<Record*, SubRegMap> SubRegMaps;
+
+ SubRegMaps SubReg;
+ SubRegMap &inferSubRegIndices(Record *Reg);
+
+ // Composite SubRegIndex instances.
+ // Map (SubRegIndex,SubRegIndex) -> SubRegIndex
+ typedef DenseMap<std::pair<Record*,Record*>,Record*> CompositeMap;
+ CompositeMap Composite;
+
+ // Compute SubRegIndex compositions after inferSubRegIndices has run on all
+ // registers.
+ void computeComposites();
+};
// Calculate all subregindices for Reg. Loopy subregs cause infinite recursion.
-static SubRegMap &inferSubRegIndices(Record *Reg, AllSubRegMap &ASRM) {
- SubRegMap &SRM = ASRM[Reg];
+RegisterMaps::SubRegMap &RegisterMaps::inferSubRegIndices(Record *Reg) {
+ SubRegMap &SRM = SubReg[Reg];
if (!SRM.empty())
return SRM;
std::vector<Record*> SubRegs = Reg->getValueAsListOfDefs("SubRegs");
if (SubRegs.size() != Indices.size())
throw "Register " + Reg->getName() + " SubRegIndices doesn't match SubRegs";
- // First insert the direct subregs.
+ // First insert the direct subregs and make sure they are fully indexed.
for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
if (!SRM.insert(std::make_pair(Indices[i], SubRegs[i])).second)
throw "SubRegIndex " + Indices[i]->getName()
+ " appears twice in Register " + Reg->getName();
- inferSubRegIndices(SubRegs[i], ASRM);
+ inferSubRegIndices(SubRegs[i]);
}
+ // Keep track of inherited subregs and how they can be reached.
+ // Register -> (SubRegIndex, SubRegIndex)
+ typedef std::map<Record*, std::pair<Record*,Record*>, LessRecord> OrphanMap;
+ OrphanMap Orphans;
+
// Clone inherited subregs. Here the order is important - earlier subregs take
// precedence.
for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
- SubRegMap &M = ASRM[SubRegs[i]];
- SRM.insert(M.begin(), M.end());
+ SubRegMap &M = SubReg[SubRegs[i]];
+ for (SubRegMap::iterator si = M.begin(), se = M.end(); si != se; ++si)
+ if (!SRM.insert(*si).second)
+ Orphans[si->second] = std::make_pair(Indices[i], si->first);
}
// Finally process the composites.
DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
throw "Invalid SubClassIndex in " + Pat->getAsString();
- SubRegMap::const_iterator ni = ASRM[R2].find(IdxInit->getDef());
- if (ni == ASRM[R2].end())
+ SubRegMap::const_iterator ni = SubReg[R2].find(IdxInit->getDef());
+ if (ni == SubReg[R2].end())
throw "Composite " + Pat->getAsString() + " refers to bad index in "
+ R2->getName();
R2 = ni->second;
// Insert composite index. Allow overriding inherited indices etc.
SRM[BaseIdxInit->getDef()] = R2;
+
+ // R2 is now directly addressable, no longer an orphan.
+ Orphans.erase(R2);
+ }
+
+ // Now, Orphans contains the inherited subregisters without a direct index.
+ if (!Orphans.empty()) {
+ errs() << "Error: Register " << getQualifiedName(Reg)
+ << " inherited subregisters without an index:\n";
+ for (OrphanMap::iterator i = Orphans.begin(), e = Orphans.end(); i != e;
+ ++i) {
+ errs() << " " << getQualifiedName(i->first)
+ << " = " << i->second.first->getName()
+ << ", " << i->second.second->getName() << "\n";
+ }
+ abort();
}
return SRM;
}
+void RegisterMaps::computeComposites() {
+ for (SubRegMaps::const_iterator sri = SubReg.begin(), sre = SubReg.end();
+ sri != sre; ++sri) {
+ Record *Reg1 = sri->first;
+ const SubRegMap &SRM1 = sri->second;
+ for (SubRegMap::const_iterator i1 = SRM1.begin(), e1 = SRM1.end();
+ i1 != e1; ++i1) {
+ Record *Idx1 = i1->first;
+ Record *Reg2 = i1->second;
+ // Ignore identity compositions.
+ if (Reg1 == Reg2)
+ continue;
+ // If Reg2 has no subregs, Idx1 doesn't compose.
+ if (!SubReg.count(Reg2))
+ continue;
+ const SubRegMap &SRM2 = SubReg[Reg2];
+ // Try composing Idx1 with another SubRegIndex.
+ for (SubRegMap::const_iterator i2 = SRM2.begin(), e2 = SRM2.end();
+ i2 != e2; ++i2) {
+ std::pair<Record*,Record*> IdxPair(Idx1, i2->first);
+ Record *Reg3 = i2->second;
+ // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
+ for (SubRegMap::const_iterator i1d = SRM1.begin(), e1d = SRM1.end();
+ i1d != e1d; ++i1d) {
+ // Ignore identity compositions.
+ if (Reg2 == Reg3)
+ continue;
+ if (i1d->second == Reg3) {
+ std::pair<CompositeMap::iterator,bool> Ins =
+ Composite.insert(std::make_pair(IdxPair, i1d->first));
+ // Conflicting composition?
+ if (!Ins.second && Ins.first->second != i1d->first) {
+ errs() << "Error: SubRegIndex " << getQualifiedName(Idx1)
+ << " and " << getQualifiedName(IdxPair.second)
+ << " compose ambiguously as "
+ << getQualifiedName(Ins.first->second) << " or "
+ << getQualifiedName(i1d->first) << "\n";
+ abort();
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
+ // compositions, so remove any mappings of that form.
+ for (CompositeMap::iterator i = Composite.begin(), e = Composite.end();
+ i != e;) {
+ CompositeMap::iterator j = i;
+ ++i;
+ if (j->first.second == j->second)
+ Composite.erase(j);
+ }
+}
+
class RegisterSorter {
private:
std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs;
// RegisterInfoEmitter::run - Main register file description emitter.
//
void RegisterInfoEmitter::run(raw_ostream &OS) {
- CodeGenTarget Target;
+ CodeGenTarget Target(Records);
EmitSourceFileHeader("Register Information Source Fragment", OS);
OS << "namespace llvm {\n\n";
// Give the register class a legal C name if it's anonymous.
std::string Name = RC.TheDef->getName();
-
+
// Emit the register list now.
OS << " // " << Name << " Register Class...\n"
<< " static const unsigned " << Name
// Emit the ValueType arrays for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc];
-
+
// Give the register class a legal C name if it's anonymous.
std::string Name = RC.TheDef->getName() + "VTs";
-
+
// Emit the register list now.
- OS << " // " << Name
+ OS << " // " << Name
<< " Register Class Value Types...\n"
<< " static const EVT " << Name
<< "[] = {\n ";
OS << "MVT::Other\n };\n\n";
}
OS << "} // end anonymous namespace\n\n";
-
+
// Now that all of the structs have been emitted, emit the instances.
if (!RegisterClasses.empty()) {
OS << "namespace " << RegisterClasses[0].Namespace
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
OS << " " << RegisterClasses[i].getName() << "Class\t"
<< RegisterClasses[i].getName() << "RegClass;\n";
-
+
std::map<unsigned, std::set<unsigned> > SuperClassMap;
std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
OS << "\n";
// Give the register class a legal C name if it's anonymous.
std::string Name = RC.TheDef->getName();
- std::set<Record*> RegSet;
- for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
- Record *Reg = RC.Elements[i];
- RegSet.insert(Reg);
- }
-
- OS << " // " << Name
+ OS << " // " << Name
<< " Register Class sub-classes...\n"
<< " static const TargetRegisterClass* const "
<< Name << "Subclasses[] = {\n ";
for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
- // RC2 is a sub-class of RC if it is a valid replacement for any
- // instruction operand where an RC register is required. It must satisfy
- // these conditions:
- //
- // 1. All RC2 registers are also in RC.
- // 2. The RC2 spill size must not be smaller that the RC spill size.
- // 3. RC2 spill alignment must be compatible with RC.
- //
// Sub-classes are used to determine if a virtual register can be used
// as an instruction operand, or if it must be copied first.
+ if (rc == rc2 || !RC.hasSubClass(&RC2)) continue;
- if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
- (RC.SpillAlignment && RC2.SpillAlignment % RC.SpillAlignment) ||
- RC.SpillSize > RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
- continue;
-
if (!Empty) OS << ", ";
OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
Empty = false;
// Give the register class a legal C name if it's anonymous.
std::string Name = RC.TheDef->getName();
- OS << " // " << Name
+ OS << " // " << Name
<< " Register Class super-classes...\n"
<< " static const TargetRegisterClass* const "
<< Name << "Superclasses[] = {\n ";
const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
if (!Empty) OS << ", ";
OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
- Empty = false;
+ Empty = false;
}
}
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
const CodeGenRegisterClass &RC = RegisterClasses[i];
OS << RC.MethodBodies << "\n";
- OS << RC.getName() << "Class::" << RC.getName()
+ OS << RC.getName() << "Class::" << RC.getName()
<< "Class() : TargetRegisterClass("
<< RC.getName() + "RegClassID" << ", "
<< '\"' << RC.getName() << "\", "
<< RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size()
<< ") {}\n";
}
-
+
OS << "}\n";
}
std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases;
typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
DwarfRegNumsMapTy DwarfRegNums;
-
+
const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
RegisterAliases);
}
}
-
+
// Print the SubregHashTable, a simple quadratically probed
// hash table for determining if a register is a subregister
// of another register.
RegNo[Regs[i].TheDef] = i;
NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size();
}
-
+
unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs);
unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize];
std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U);
-
+
unsigned hashMisses = 0;
-
+
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
Record* R = Regs[i].TheDef;
for (std::set<Record*>::iterator I = RegisterSubRegs[R].begin(),
SubregHashTable[index*2+1] != ~0U) {
index = (index + ProbeAmt) & (SubregHashTableSize-1);
ProbeAmt += 2;
-
+
hashMisses++;
}
-
+
SubregHashTable[index*2] = i;
SubregHashTable[index*2+1] = RegNo[RJ];
}
}
-
+
OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
-
+
if (SubregHashTableSize) {
std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
-
+
OS << " const unsigned SubregHashTable[] = { ";
for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) {
if (i != 0)
// Insert spaces for nice formatting.
OS << " ";
-
+
if (SubregHashTable[2*i] != ~0U) {
OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", "
<< getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n";
OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
}
}
-
+
unsigned Idx = SubregHashTableSize*2-2;
if (SubregHashTable[Idx] != ~0U) {
OS << " "
} else {
OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
}
-
+
OS << " const unsigned SubregHashTableSize = "
<< SubregHashTableSize << ";\n";
} else {
OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n"
<< " const unsigned SubregHashTableSize = 1;\n";
}
-
+
delete [] SubregHashTable;
RegNo[Regs[i].TheDef] = i;
NumAliases += RegisterAliases[Regs[i].TheDef].size();
}
-
+
unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases);
unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize];
std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U);
-
+
hashMisses = 0;
-
+
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
Record* R = Regs[i].TheDef;
for (std::set<Record*>::iterator I = RegisterAliases[R].begin(),
AliasesHashTable[index*2+1] != ~0U) {
index = (index + ProbeAmt) & (AliasesHashTableSize-1);
ProbeAmt += 2;
-
+
hashMisses++;
}
-
+
AliasesHashTable[index*2] = i;
AliasesHashTable[index*2+1] = RegNo[RJ];
}
}
-
+
OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
-
+
if (AliasesHashTableSize) {
std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
-
+
OS << " const unsigned AliasesHashTable[] = { ";
for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) {
if (i != 0)
// Insert spaces for nice formatting.
OS << " ";
-
+
if (AliasesHashTable[2*i] != ~0U) {
OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", "
<< getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n";
OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
}
}
-
+
unsigned Idx = AliasesHashTableSize*2-2;
if (AliasesHashTable[Idx] != ~0U) {
OS << " "
} else {
OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
}
-
+
OS << " const unsigned AliasesHashTableSize = "
<< AliasesHashTableSize << ";\n";
} else {
OS << " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n"
<< " const unsigned AliasesHashTableSize = 1;\n";
}
-
+
delete [] AliasesHashTable;
if (!RegisterAliases.empty())
- OS << "\n\n // Register Alias Sets...\n";
+ OS << "\n\n // Register Overlap Lists...\n";
- // Emit the empty alias list
- OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
- // Loop over all of the registers which have aliases, emitting the alias list
- // to memory.
+ // Emit an overlap list for all registers.
for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
- OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
+ OS << " const unsigned " << I->first->getName() << "_Overlaps[] = { "
+ << getQualifiedName(I->first) << ", ";
for (std::set<Record*>::iterator ASI = I->second.begin(),
E = I->second.end(); ASI != E; ++ASI)
OS << getQualifiedName(*ASI) << ", ";
// sub-registers list to memory.
for (std::map<Record*, std::set<Record*>, LessRecord>::iterator
I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
+ if (I->second.empty())
+ continue;
OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
std::vector<Record*> SubRegsVector;
for (std::set<Record*>::iterator ASI = I->second.begin(),
// super-registers list to memory.
for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
+ if (I->second.empty())
+ continue;
OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
std::vector<Record*> SuperRegsVector;
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = Regs[i];
OS << " { \"";
- OS << Reg.getName() << "\",\t";
- if (RegisterAliases.count(Reg.TheDef))
- OS << Reg.getName() << "_AliasSet,\t";
- else
- OS << "Empty_AliasSet,\t";
- if (RegisterSubRegs.count(Reg.TheDef))
+ OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
+ if (!RegisterSubRegs[Reg.TheDef].empty())
OS << Reg.getName() << "_SubRegsSet,\t";
else
OS << "Empty_SubRegsSet,\t";
- if (RegisterSuperRegs.count(Reg.TheDef))
+ if (!RegisterSuperRegs[Reg.TheDef].empty())
OS << Reg.getName() << "_SuperRegsSet },\n";
else
OS << "Empty_SuperRegsSet },\n";
std::string ClassName = Target.getName() + "GenRegisterInfo";
// Calculate the mapping of subregister+index pairs to physical registers.
- AllSubRegMap AllSRM;
+ RegisterMaps RegMaps;
// Emit the subregister + index mapping function based on the information
// calculated above.
<< " switch (RegNo) {\n"
<< " default:\n return 0;\n";
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- SubRegMap &SRM = inferSubRegIndices(Regs[i].TheDef, AllSRM);
+ RegisterMaps::SubRegMap &SRM = RegMaps.inferSubRegIndices(Regs[i].TheDef);
if (SRM.empty())
continue;
OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
OS << " switch (Index) {\n";
OS << " default: return 0;\n";
- for (SubRegMap::const_iterator ii = SRM.begin(), ie = SRM.end(); ii != ie;
- ++ii)
+ for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(),
+ ie = SRM.end(); ii != ie; ++ii)
OS << " case " << getQualifiedName(ii->first)
<< ": return " << getQualifiedName(ii->second) << ";\n";
OS << " };\n" << " break;\n";
<< " switch (RegNo) {\n"
<< " default:\n return 0;\n";
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- SubRegMap &SRM = AllSRM[Regs[i].TheDef];
+ RegisterMaps::SubRegMap &SRM = RegMaps.SubReg[Regs[i].TheDef];
if (SRM.empty())
continue;
OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
- for (SubRegMap::const_iterator ii = SRM.begin(), ie = SRM.end(); ii != ie;
- ++ii)
+ for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(),
+ ie = SRM.end(); ii != ie; ++ii)
OS << " if (SubRegNo == " << getQualifiedName(ii->second)
<< ") return " << getQualifiedName(ii->first) << ";\n";
OS << " return 0;\n";
OS << " };\n";
OS << " return 0;\n";
OS << "}\n\n";
-
+
+ // Emit composeSubRegIndices
+ RegMaps.computeComposites();
+ OS << "unsigned " << ClassName
+ << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
+ << " switch (IdxA) {\n"
+ << " default:\n return IdxB;\n";
+ for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
+ bool Open = false;
+ for (unsigned j = 0; j != e; ++j) {
+ if (Record *Comp = RegMaps.Composite.lookup(
+ std::make_pair(SubRegIndices[i], SubRegIndices[j]))) {
+ if (!Open) {
+ OS << " case " << getQualifiedName(SubRegIndices[i])
+ << ": switch(IdxB) {\n default: return IdxB;\n";
+ Open = true;
+ }
+ OS << " case " << getQualifiedName(SubRegIndices[j])
+ << ": return " << getQualifiedName(Comp) << ";\n";
+ }
+ }
+ if (Open)
+ OS << " }\n";
+ }
+ OS << " }\n}\n\n";
+
// Emit the constructor of the class...
OS << ClassName << "::" << ClassName
<< "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
}
// Now we know maximal length of number list. Append -1's, where needed
- for (DwarfRegNumsMapTy::iterator
+ for (DwarfRegNumsMapTy::iterator
I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
I->second.push_back(-1);
<< " default:\n"
<< " assert(0 && \"Unknown DWARF flavour\");\n"
<< " return -1;\n";
-
+
for (unsigned i = 0, e = maxLength; i != e; ++i) {
OS << " case " << i << ":\n"
<< " switch (RegNum) {\n"
<< " default:\n"
<< " assert(0 && \"Invalid RegNum\");\n"
<< " return -1;\n";
-
+
// Sort by name to get a stable order.
-
- for (DwarfRegNumsMapTy::iterator
+
+ for (DwarfRegNumsMapTy::iterator
I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
int RegNo = I->second[i];
if (RegNo != -2)
}
OS << " };\n";
}
-
+
OS << " };\n}\n\n";
OS << "} // End llvm namespace \n";