//
// The LLVM Compiler Infrastructure
//
-// This file was developed by James M. Laskey and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#include <algorithm>
using namespace llvm;
-//
-// Convenience types.
-//
-typedef std::vector<Record*> RecordList;
-
-//
-// RecordListIter - Simplify iterating through a std::vector of records.
-//
-class RecordListIter {
- std::vector<Record*>::iterator RI; // Currect cursor
- std::vector<Record*>::iterator E; // End point
-
-public:
-
- //
- // Ctor.
- //
- RecordListIter(RecordList &RL)
- : RI(RL.begin()), E(RL.end())
- {}
-
-
- //
- // isMore - Return true if more records are available.
- //
- bool isMore() const { return RI != E; }
-
- //
- // next - Return the next record or NULL if none.
- //
- Record *next() { return isMore() ? *RI++ : NULL; }
-};
-
-//
-// DefListIter - Simplify iterating through a field which is a list of records.
-//
-struct DefListIter {
- ListInit *List; // List of DefInit
- unsigned N; // Number of elements in list
- unsigned i; // Current index in list
-
- //
- // Ctor - Lookup field and get list and length.
- //
- DefListIter(Record *R, const std::string &Name)
- : List(R->getValueAsListInit(Name)), N(List->getSize()), i(0)
- {}
-
- //
- // isMore - Return true if more records are available.
- //
- bool isMore() const { return i < N; }
-
- //
- // next - Return the next record or NULL if none.
- //
- Record *next() {
- if (isMore()) {
- if (DefInit *DI = dynamic_cast<DefInit*>(List->getElement(i++))) {
- return DI->getDef();
- }
- }
- return NULL;
- }
-};
-
-//
-// Record sort by name function.
-//
-struct LessRecord {
- bool operator()(const Record *Rec1, const Record *Rec2) const {
- return Rec1->getName() < Rec2->getName();
- }
-};
-
-//
-// Record sort by field "Name" function.
-//
-struct LessRecordFieldName {
- bool operator()(const Record *Rec1, const Record *Rec2) const {
- return Rec1->getValueAsString("Name") < Rec2->getValueAsString("Name");
- }
-};
-
//
// Enumeration - Emit the specified class as an enumeration.
//
const char *ClassName,
bool isBits) {
// Get all records of class and sort
- RecordList Defs = Records.getAllDerivedDefinitions(ClassName);
- sort(Defs.begin(), Defs.end(), LessRecord());
+ std::vector<Record*> DefList = Records.getAllDerivedDefinitions(ClassName);
+ std::sort(DefList.begin(), DefList.end(), LessRecord());
- // Track position if isBits
- int i = 0;
-
// Open enumeration
OS << "enum {\n";
// For each record
- RecordListIter DI(Defs);
- while (Record *R = DI.next()) {
+ for (unsigned i = 0, N = DefList.size(); i < N;) {
+ // Next record
+ Record *Def = DefList[i];
+
// Get and emit name
- std::string Name = R->getName();
- OS << " " << Name;
+ OS << " " << Def->getName();
// If bit flags then emit expression (1 << i)
- if (isBits) OS << " = " << " 1 << " << i++;
+ if (isBits) OS << " = " << " 1 << " << i;
- // Depending on if more in the list, emit comma and new line
- OS << (DI.isMore() ? ",\n" : "\n");
+ // Depending on 'if more in the list' emit comma
+ if (++i < N) OS << ",";
+
+ OS << "\n";
}
// Close enumeration
}
//
-// FeatureKeyValues - Emit data of all the subtarget features. Used by command
-// line.
+// FeatureKeyValues - Emit data of all the subtarget features. Used by the
+// command line.
//
void SubtargetEmitter::FeatureKeyValues(std::ostream &OS) {
// Gather and sort all the features
- RecordList Features = Records.getAllDerivedDefinitions("SubtargetFeature");
- sort(Features.begin(), Features.end(), LessRecord());
+ std::vector<Record*> FeatureList =
+ Records.getAllDerivedDefinitions("SubtargetFeature");
+ std::sort(FeatureList.begin(), FeatureList.end(), LessRecordFieldName());
// Begin feature table
OS << "// Sorted (by key) array of values for CPU features.\n"
- << "static llvm::SubtargetFeatureKV FeatureKV[] = {\n";
+ << "static const llvm::SubtargetFeatureKV FeatureKV[] = {\n";
// For each feature
- RecordListIter FI(Features);
- while (Record *R = FI.next()) {
- std::string Instance = R->getName();
- std::string Name = R->getValueAsString("Name");
- std::string Desc = R->getValueAsString("Desc");
+ for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) {
+ // Next feature
+ Record *Feature = FeatureList[i];
+
+ const std::string &Name = Feature->getName();
+ const std::string &CommandLineName = Feature->getValueAsString("Name");
+ const std::string &Desc = Feature->getValueAsString("Desc");
+
+ if (CommandLineName.empty()) continue;
- // Emit as { "feature", "decription", feactureEnum }
+ // Emit as { "feature", "decription", feactureEnum, i1 | i2 | ... | in }
OS << " { "
- << "\"" << Name << "\", "
+ << "\"" << CommandLineName << "\", "
<< "\"" << Desc << "\", "
- << Instance
- << (FI.isMore() ? " },\n" : " }\n");
+ << Name << ", ";
+
+ const std::vector<Record*> &ImpliesList =
+ Feature->getValueAsListOfDefs("Implies");
+
+ if (ImpliesList.empty()) {
+ OS << "0";
+ } else {
+ for (unsigned j = 0, M = ImpliesList.size(); j < M;) {
+ OS << ImpliesList[j]->getName();
+ if (++j < M) OS << " | ";
+ }
+ }
+
+ OS << " }";
+
+ // Depending on 'if more in the list' emit comma
+ if ((i + 1) < N) OS << ",";
+
+ OS << "\n";
}
// End feature table
//
void SubtargetEmitter::CPUKeyValues(std::ostream &OS) {
// Gather and sort processor information
- RecordList Processors = Records.getAllDerivedDefinitions("Processor");
- sort(Processors.begin(), Processors.end(), LessRecordFieldName());
+ std::vector<Record*> ProcessorList =
+ Records.getAllDerivedDefinitions("Processor");
+ std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
// Begin processor table
OS << "// Sorted (by key) array of values for CPU subtype.\n"
<< "static const llvm::SubtargetFeatureKV SubTypeKV[] = {\n";
// For each processor
- RecordListIter PI(Processors);
- while (Record *R = PI.next()) {
- std::string Name = R->getValueAsString("Name");
- DefListIter FI(R, "Features");
+ for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
+ // Next processor
+ Record *Processor = ProcessorList[i];
+
+ const std::string &Name = Processor->getValueAsString("Name");
+ const std::vector<Record*> &FeatureList =
+ Processor->getValueAsListOfDefs("Features");
// Emit as { "cpu", "description", f1 | f2 | ... fn },
OS << " { "
<< "\"" << Name << "\", "
<< "\"Select the " << Name << " processor\", ";
- if (!FI.isMore()) {
+ if (FeatureList.empty()) {
OS << "0";
} else {
- while (Record *Feature = FI.next()) {
- std::string Name = Feature->getName();
- OS << Name;
- if (FI.isMore()) OS << " | ";
+ for (unsigned j = 0, M = FeatureList.size(); j < M;) {
+ OS << FeatureList[j]->getName();
+ if (++j < M) OS << " | ";
}
}
- OS << (PI.isMore() ? " },\n" : " }\n");
+ // The "0" is for the "implies" section of this data structure.
+ OS << ", 0 }";
+
+ // Depending on 'if more in the list' emit comma
+ if (++i < N) OS << ",";
+
+ OS << "\n";
}
// End processor table
// CollectAllItinClasses - Gathers and enumerates all the itinerary classes.
// Returns itinerary class count.
//
-unsigned SubtargetEmitter::CollectAllItinClasses(IntMap &ItinClassesMap) {
+unsigned SubtargetEmitter::CollectAllItinClasses(std::ostream &OS,
+ std::map<std::string, unsigned> &ItinClassesMap) {
// Gather and sort all itinerary classes
- RecordList ICL = Records.getAllDerivedDefinitions("InstrItinClass");
- sort(ICL.begin(), ICL.end(), LessRecord());
-
- // Track enumeration
- unsigned Index = 0;
-
- // For each class
- RecordListIter ICI(ICL);
- while (Record *ItinClass = ICI.next()) {
+ std::vector<Record*> ItinClassList =
+ Records.getAllDerivedDefinitions("InstrItinClass");
+ std::sort(ItinClassList.begin(), ItinClassList.end(), LessRecord());
+
+ // For each itinerary class
+ unsigned N = ItinClassList.size();
+ for (unsigned i = 0; i < N; i++) {
+ // Next itinerary class
+ const Record *ItinClass = ItinClassList[i];
// Get name of itinerary class
- std::string Name = ItinClass->getName();
// Assign itinerary class a unique number
- ItinClassesMap[Name] = Index++;
+ ItinClassesMap[ItinClass->getName()] = i;
}
+ // Emit size of table
+ OS<<"\nenum {\n";
+ OS<<" ItinClassesSize = " << N << "\n";
+ OS<<"};\n";
+
// Return itinerary class count
- return Index;
+ return N;
}
//
//
void SubtargetEmitter::FormItineraryString(Record *ItinData,
std::string &ItinString,
- unsigned &N) {
- // Set up stages iterator
- DefListIter SLI(ItinData, "Stages");
- // Get stage count
- N = SLI.N;
+ unsigned &NStages) {
+ // Get states list
+ const std::vector<Record*> &StageList =
+ ItinData->getValueAsListOfDefs("Stages");
// For each stage
- while (Record *Stage = SLI.next()) {
+ unsigned N = NStages = StageList.size();
+ for (unsigned i = 0; i < N;) {
+ // Next stage
+ const Record *Stage = StageList[i];
+
// Form string as ,{ cycles, u1 | u2 | ... | un }
int Cycles = Stage->getValueAsInt("Cycles");
- ItinString += " ,{ " + itostr(Cycles) + ", ";
+ ItinString += " { " + itostr(Cycles) + ", ";
+
+ // Get unit list
+ const std::vector<Record*> &UnitList = Stage->getValueAsListOfDefs("Units");
// For each unit
- DefListIter ULI(Stage, "Units");
- while (Record *Unit = ULI.next()) {
- std::string Name = Unit->getName();
- ItinString += Name;
- if (ULI.isMore())ItinString += " | ";
+ for (unsigned j = 0, M = UnitList.size(); j < M;) {
+ // Add name and bitwise or
+ ItinString += UnitList[j]->getName();
+ if (++j < M) ItinString += " | ";
}
// Close off stage
ItinString += " }";
+ if (++i < N) ItinString += ", ";
}
}
// processors.
//
void SubtargetEmitter::EmitStageData(std::ostream &OS,
- unsigned N,
- IntMap &ItinClassesMap,
- ProcessorList &ProcList) {
+ unsigned NItinClasses,
+ std::map<std::string, unsigned> &ItinClassesMap,
+ std::vector<std::vector<InstrItinerary> > &ProcList) {
// Gather processor iteraries
- RecordList Itins = Records.getAllDerivedDefinitions("ProcessorItineraries");
+ std::vector<Record*> ProcItinList =
+ Records.getAllDerivedDefinitions("ProcessorItineraries");
// If just no itinerary then don't bother
- if (Itins.size() < 2) return;
+ if (ProcItinList.size() < 2) return;
// Begin stages table
- OS << "static llvm::InstrStage Stages[] = {\n"
- " { 0, 0 } // No itinerary\n";
+ OS << "static const llvm::InstrStage Stages[] = {\n"
+ " { 0, 0 }, // No itinerary\n";
- IntMap ItinMap;
- unsigned Index = 1;
- RecordListIter II(Itins);
- while (Record *Itin = II.next()) {
+ unsigned StageCount = 1;
+ unsigned ItinEnum = 1;
+ std::map<std::string, unsigned> ItinMap;
+ for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
+ // Next record
+ Record *Proc = ProcItinList[i];
+
// Get processor itinerary name
- std::string Name = Itin->getName();
+ const std::string &Name = Proc->getName();
// Skip default
if (Name == "NoItineraries") continue;
// Create and expand processor itinerary to cover all itinerary classes
- IntineraryList IL;
- IL.resize(N);
+ std::vector<InstrItinerary> ItinList;
+ ItinList.resize(NItinClasses);
+
+ // Get itinerary data list
+ std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
- // For each itinerary
- DefListIter IDLI(Itin, "IID");
- while (Record *ItinData = IDLI.next()) {
+ // For each itinerary data
+ for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) {
+ // Next itinerary data
+ Record *ItinData = ItinDataList[j];
+
// Get string and stage count
std::string ItinString;
- unsigned M;
- FormItineraryString(ItinData, ItinString, M);
+ unsigned NStages;
+ FormItineraryString(ItinData, ItinString, NStages);
// Check to see if it already exists
unsigned Find = ItinMap[ItinString];
// If new itinerary
if (Find == 0) {
- // Emit as ,{ cycles, u1 | u2 | ... | un } // index
- OS << ItinString << " // " << Index << "\n";
- ItinMap[ItinString] = Find = Index++;
+ // Emit as { cycles, u1 | u2 | ... | un }, // index
+ OS << ItinString << ", // " << ItinEnum << "\n";
+ // Record Itin class number.
+ ItinMap[ItinString] = Find = StageCount;
+ StageCount += NStages;
+ ItinEnum++;
}
// Set up itinerary as location and location + stage count
- InstrItinerary Intinerary = { Find, Find + M };
+ InstrItinerary Intinerary = { Find, Find + NStages };
// Locate where to inject into processor itinerary table
- std::string Name = ItinData->getValueAsDef("TheClass")->getName();
+ const std::string &Name = ItinData->getValueAsDef("TheClass")->getName();
Find = ItinClassesMap[Name];
// Inject - empty slots will be 0, 0
- IL[Find] = Intinerary;
+ ItinList[Find] = Intinerary;
}
// Add process itinerary to list
- ProcList.push_back(IL);
+ ProcList.push_back(ItinList);
}
+ // Closing stage
+ OS << " { 0, 0 } // End itinerary\n";
// End stages table
OS << "};\n";
+
+ // Emit size of table
+ OS<<"\nenum {\n";
+ OS<<" StagesSize = sizeof(Stages)/sizeof(llvm::InstrStage)\n";
+ OS<<"};\n";
}
//
-// EmitProcessData - Generate data for processor itineraries.
+// EmitProcessorData - Generate data for processor itineraries.
//
-void SubtargetEmitter::EmitProcessData(std::ostream &OS,
- ProcessorList &ProcList) {
+void SubtargetEmitter::EmitProcessorData(std::ostream &OS,
+ std::vector<std::vector<InstrItinerary> > &ProcList) {
// Get an iterator for processor itinerary stages
- ProcessorList::iterator PLI = ProcList.begin();
+ std::vector<std::vector<InstrItinerary> >::iterator
+ ProcListIter = ProcList.begin();
// For each processor itinerary
- RecordList Itins = Records.getAllDerivedDefinitions("ProcessorItineraries");
- RecordListIter II(Itins);
- while (Record *Itin = II.next()) {
+ std::vector<Record*> Itins =
+ Records.getAllDerivedDefinitions("ProcessorItineraries");
+ for (unsigned i = 0, N = Itins.size(); i < N; i++) {
+ // Next record
+ Record *Itin = Itins[i];
+
// Get processor itinerary name
- std::string Name = Itin->getName();
+ const std::string &Name = Itin->getName();
// Skip default
if (Name == "NoItineraries") continue;
// Begin processor itinerary table
OS << "\n";
- OS << "static llvm::InstrItinerary " << Name << "[] = {\n";
+ OS << "static const llvm::InstrItinerary " << Name << "[] = {\n";
// For each itinerary class
- IntineraryList &IL = *PLI++;
- unsigned Index = 0;
- for (IntineraryList::iterator ILI = IL.begin(), E = IL.end(); ILI != E;) {
- InstrItinerary &Intinerary = *ILI++;
+ std::vector<InstrItinerary> &ItinList = *ProcListIter++;
+ for (unsigned j = 0, M = ItinList.size(); j < M;) {
+ InstrItinerary &Intinerary = ItinList[j];
// Emit in the form of { first, last } // index
if (Intinerary.First == 0) {
OS << " { " << Intinerary.First << ", " << Intinerary.Last << " }";
}
- if (ILI != E) OS << ",";
- OS << " // " << Index++ << "\n";
+ // If more in list add comma
+ if (++j < M) OS << ",";
+
+ OS << " // " << (j - 1) << "\n";
}
// End processor itinerary table
}
}
+//
+// EmitProcessorLookup - generate cpu name to itinerary lookup table.
+//
+void SubtargetEmitter::EmitProcessorLookup(std::ostream &OS) {
+ // Gather and sort processor information
+ std::vector<Record*> ProcessorList =
+ Records.getAllDerivedDefinitions("Processor");
+ std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
+
+ // Begin processor table
+ OS << "\n";
+ OS << "// Sorted (by key) array of itineraries for CPU subtype.\n"
+ << "static const llvm::SubtargetInfoKV ProcItinKV[] = {\n";
+
+ // For each processor
+ for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
+ // Next processor
+ Record *Processor = ProcessorList[i];
+
+ const std::string &Name = Processor->getValueAsString("Name");
+ const std::string &ProcItin =
+ Processor->getValueAsDef("ProcItin")->getName();
+
+ // Emit as { "cpu", procinit },
+ OS << " { "
+ << "\"" << Name << "\", "
+ << "(void *)&" << ProcItin;
+
+ OS << " }";
+
+ // Depending on ''if more in the list'' emit comma
+ if (++i < N) OS << ",";
+
+ OS << "\n";
+ }
+
+ // End processor table
+ OS << "};\n";
+
+ // Emit size of table
+ OS<<"\nenum {\n";
+ OS<<" ProcItinKVSize = sizeof(ProcItinKV)/"
+ "sizeof(llvm::SubtargetInfoKV)\n";
+ OS<<"};\n";
+}
+
//
// EmitData - Emits all stages and itineries, folding common patterns.
//
void SubtargetEmitter::EmitData(std::ostream &OS) {
- IntMap ItinClassesMap;
- ProcessorList ProcList;
+ std::map<std::string, unsigned> ItinClassesMap;
+ std::vector<std::vector<InstrItinerary> > ProcList;
// Enumerate all the itinerary classes
- unsigned N = CollectAllItinClasses(ItinClassesMap);
- // Emit the stage data
- EmitStageData(OS, N, ItinClassesMap, ProcList);
- // Emit the processor itinerary data
- EmitProcessData(OS, ProcList);
+ unsigned NItinClasses = CollectAllItinClasses(OS, ItinClassesMap);
+ // Make sure the rest is worth the effort
+ HasItineraries = NItinClasses != 1; // Ignore NoItinerary.
+
+ if (HasItineraries) {
+ // Emit the stage data
+ EmitStageData(OS, NItinClasses, ItinClassesMap, ProcList);
+ // Emit the processor itinerary data
+ EmitProcessorData(OS, ProcList);
+ // Emit the processor lookup data
+ EmitProcessorLookup(OS);
+ }
}
//
// the subtarget features string.
//
void SubtargetEmitter::ParseFeaturesFunction(std::ostream &OS) {
- RecordList Features = Records.getAllDerivedDefinitions("SubtargetFeature");
- sort(Features.begin(), Features.end(), LessRecord());
+ std::vector<Record*> Features =
+ Records.getAllDerivedDefinitions("SubtargetFeature");
+ std::sort(Features.begin(), Features.end(), LessRecord());
OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
- "// subtarget options.\n"
- "void llvm::";
+ << "// subtarget options.\n"
+ << "void llvm::";
OS << Target;
OS << "Subtarget::ParseSubtargetFeatures(const std::string &FS,\n"
- " const std::string &CPU) {\n"
- " SubtargetFeatures Features(FS);\n"
- " Features.setCPUIfNone(CPU);\n"
- " uint32_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize,\n"
- " FeatureKV, FeatureKVSize);\n";
-
- RecordListIter FI(Features);
- while (Record *R = FI.next()) {
- std::string Instance = R->getName();
- std::string Name = R->getValueAsString("Name");
- std::string Type = R->getValueAsString("Type");
- std::string Attribute = R->getValueAsString("Attribute");
-
- OS << " " << Attribute << " = (Bits & " << Instance << ") != 0;\n";
+ << " const std::string &CPU) {\n"
+ << " SubtargetFeatures Features(FS);\n"
+ << " Features.setCPUIfNone(CPU);\n"
+ << " uint32_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize,\n"
+ << " FeatureKV, FeatureKVSize);\n";
+
+ for (unsigned i = 0; i < Features.size(); i++) {
+ // Next record
+ Record *R = Features[i];
+ const std::string &Instance = R->getName();
+ const std::string &Value = R->getValueAsString("Value");
+ const std::string &Attribute = R->getValueAsString("Attribute");
+
+ if (Value=="true" || Value=="false")
+ OS << " if ((Bits & " << Instance << ") != 0) "
+ << Attribute << " = " << Value << ";\n";
+ else
+ OS << " if ((Bits & " << Instance << ") != 0 && " << Attribute <<
+ " < " << Value << ") " << Attribute << " = " << Value << ";\n";
}
+
+ if (HasItineraries) {
+ OS << "\n"
+ << " InstrItinerary *Itinerary = (InstrItinerary *)"
+ << "Features.getInfo(ProcItinKV, ProcItinKVSize);\n"
+ << " InstrItins = InstrItineraryData(Stages, Itinerary);\n";
+ }
+
OS << "}\n";
}
projects / oota-llvm.git / blobdiff