Record *SuperDef = 0;
unsigned SuperIdx = 0;
unsigned NumUnits = 0;
- bool IsBuffered = true;
+ int BufferSize = PRDef->getValueAsInt("BufferSize");
if (PRDef->isSubClassOf("ProcResGroup")) {
RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources");
for (RecIter RUI = ResUnits.begin(), RUE = ResUnits.end();
RUI != RUE; ++RUI) {
- if (!NumUnits)
- IsBuffered = (*RUI)->getValueAsBit("Buffered");
- else if(IsBuffered != (*RUI)->getValueAsBit("Buffered"))
- PrintFatalError(PRDef->getLoc(),
- "Mixing buffered and unbuffered resources.");
NumUnits += (*RUI)->getValueAsInt("NumUnits");
}
}
SuperIdx = ProcModel.getProcResourceIdx(SuperDef);
}
NumUnits = PRDef->getValueAsInt("NumUnits");
- IsBuffered = PRDef->getValueAsBit("Buffered");
}
// Emit the ProcResourceDesc
if (i+1 == e)
if (PRDef->getName().size() < 15)
OS.indent(15 - PRDef->getName().size());
OS << NumUnits << ", " << SuperIdx << ", "
- << IsBuffered << "}" << Sep << " // #" << i+1;
+ << BufferSize << "}" << Sep << " // #" << i+1;
if (SuperDef)
OS << ", Super=" << SuperDef->getName();
OS << "\n";
}
// Expand an explicit list of processor resources into a full list of implied
-// resource groups that cover them.
-//
-// FIXME: Effectively consider a super-resource a group that include all of its
-// subresources to allow mixing and matching super-resources and groups.
-//
-// FIXME: Warn if two overlapping groups don't have a common supergroup.
+// resource groups and super resources that cover them.
void SubtargetEmitter::ExpandProcResources(RecVec &PRVec,
std::vector<int64_t> &Cycles,
- const CodeGenProcModel &ProcModel) {
+ const CodeGenProcModel &PM) {
// Default to 1 resource cycle.
Cycles.resize(PRVec.size(), 1);
for (unsigned i = 0, e = PRVec.size(); i != e; ++i) {
+ Record *PRDef = PRVec[i];
RecVec SubResources;
- if (PRVec[i]->isSubClassOf("ProcResGroup")) {
- SubResources = PRVec[i]->getValueAsListOfDefs("Resources");
- std::sort(SubResources.begin(), SubResources.end(), LessRecord());
- }
+ if (PRDef->isSubClassOf("ProcResGroup"))
+ SubResources = PRDef->getValueAsListOfDefs("Resources");
else {
- SubResources.push_back(PRVec[i]);
+ SubResources.push_back(PRDef);
+ PRDef = SchedModels.findProcResUnits(PRVec[i], PM);
+ for (Record *SubDef = PRDef;
+ SubDef->getValueInit("Super")->isComplete();) {
+ if (SubDef->isSubClassOf("ProcResGroup")) {
+ // Disallow this for simplicitly.
+ PrintFatalError(SubDef->getLoc(), "Processor resource group "
+ " cannot be a super resources.");
+ }
+ Record *SuperDef =
+ SchedModels.findProcResUnits(SubDef->getValueAsDef("Super"), PM);
+ PRVec.push_back(SuperDef);
+ Cycles.push_back(Cycles[i]);
+ SubDef = SuperDef;
+ }
}
- for (RecIter PRI = ProcModel.ProcResourceDefs.begin(),
- PRE = ProcModel.ProcResourceDefs.end();
+ for (RecIter PRI = PM.ProcResourceDefs.begin(),
+ PRE = PM.ProcResourceDefs.end();
PRI != PRE; ++PRI) {
- if (*PRI == PRVec[i] || !(*PRI)->isSubClassOf("ProcResGroup"))
+ if (*PRI == PRDef || !(*PRI)->isSubClassOf("ProcResGroup"))
continue;
RecVec SuperResources = (*PRI)->getValueAsListOfDefs("Resources");
- std::sort(SuperResources.begin(), SuperResources.end(), LessRecord());
RecIter SubI = SubResources.begin(), SubE = SubResources.end();
- RecIter SuperI = SuperResources.begin(), SuperE = SuperResources.end();
- for ( ; SubI != SubE && SuperI != SuperE; ++SuperI) {
- if (*SubI < *SuperI)
+ for( ; SubI != SubE; ++SubI) {
+ if (std::find(SuperResources.begin(), SuperResources.end(), *SubI)
+ == SuperResources.end()) {
break;
- else if (*SuperI < *SubI)
- continue;
- ++SubI;
+ }
}
if (SubI == SubE) {
PRVec.push_back(*PRI);
OS << "\n";
OS << "static const llvm::MCSchedModel " << PI->ModelName << "(\n";
EmitProcessorProp(OS, PI->ModelDef, "IssueWidth", ',');
- EmitProcessorProp(OS, PI->ModelDef, "MinLatency", ',');
+ EmitProcessorProp(OS, PI->ModelDef, "MicroOpBufferSize", ',');
EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ',');
EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ',');
- EmitProcessorProp(OS, PI->ModelDef, "ILPWindow", ',');
EmitProcessorProp(OS, PI->ModelDef, "MispredictPenalty", ',');
+
+ OS << " " << (bool)(PI->ModelDef ?
+ PI->ModelDef->getValueAsBit("CompleteModel") : 0)
+ << ", // " << "CompleteModel\n";
+
OS << " " << PI->Index << ", // Processor ID\n";
if (PI->hasInstrSchedModel())
OS << " " << PI->ModelName << "ProcResources" << ",\n"
for (std::vector<CodeGenSchedTransition>::const_iterator
TI = SC.Transitions.begin(), TE = SC.Transitions.end();
TI != TE; ++TI) {
- OS << " if (";
if (*PI != 0 && !std::count(TI->ProcIndices.begin(),
TI->ProcIndices.end(), *PI)) {
continue;
}
+ OS << " if (";
for (RecIter RI = TI->PredTerm.begin(), RE = TI->PredTerm.end();
RI != RE; ++RI) {
if (RI != TI->PredTerm.begin())