bool isBits) {
// Get all records of class and sort
std::vector<Record*> DefList = Records.getAllDerivedDefinitions(ClassName);
- sort(DefList.begin(), DefList.end(), LessRecord());
+ std::sort(DefList.begin(), DefList.end(), LessRecord());
// Open enumeration
OS << "enum {\n";
// If bit flags then emit expression (1 << i)
if (isBits) OS << " = " << " 1 << " << i;
- // Depending on if more in the list emit comma
+ // Depending on 'if more in the list' emit comma
if (++i < N) OS << ",";
OS << "\n";
// Gather and sort all the features
std::vector<Record*> FeatureList =
Records.getAllDerivedDefinitions("SubtargetFeature");
- sort(FeatureList.begin(), FeatureList.end(), LessRecord());
+ std::sort(FeatureList.begin(), FeatureList.end(), LessRecord());
// Begin feature table
OS << "// Sorted (by key) array of values for CPU features.\n"
<< "static llvm::SubtargetFeatureKV FeatureKV[] = {\n";
// For each feature
- for (unsigned i = 0, N = FeatureList.size(); i < N;) {
+ for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) {
// Next feature
Record *Feature = FeatureList[i];
std::string CommandLineName = Feature->getValueAsString("Name");
std::string Desc = Feature->getValueAsString("Desc");
+ if (CommandLineName.empty()) continue;
+
// Emit as { "feature", "decription", feactureEnum }
OS << " { "
<< "\"" << CommandLineName << "\", "
<< Name
<< " }";
- // Depending on if more in the list emit comma
- if (++i < N) OS << ",";
+ // Depending on 'if more in the list' emit comma
+ if ((i + 1) < N) OS << ",";
OS << "\n";
}
// Gather and sort processor information
std::vector<Record*> ProcessorList =
Records.getAllDerivedDefinitions("Processor");
- sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
+ std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
// Begin processor table
OS << "// Sorted (by key) array of values for CPU subtype.\n"
Record *Processor = ProcessorList[i];
std::string Name = Processor->getValueAsString("Name");
- std::vector<Record*> FeatureList = Processor->getValueAsListDef("Features");
+ std::vector<Record*> FeatureList =
+ Processor->getValueAsListOfDefs("Features");
// Emit as { "cpu", "description", f1 | f2 | ... fn },
OS << " { "
OS << " }";
- // Depending on if more in the list emit comma
+ // Depending on 'if more in the list' emit comma
if (++i < N) OS << ",";
OS << "\n";
// CollectAllItinClasses - Gathers and enumerates all the itinerary classes.
// Returns itinerary class count.
//
-unsigned SubtargetEmitter::CollectAllItinClasses(std::map<std::string, unsigned>
- &ItinClassesMap) {
+unsigned SubtargetEmitter::CollectAllItinClasses(std::ostream &OS,
+ std::map<std::string, unsigned> &ItinClassesMap) {
// Gather and sort all itinerary classes
std::vector<Record*> ItinClassList =
Records.getAllDerivedDefinitions("InstrItinClass");
- sort(ItinClassList.begin(), ItinClassList.end(), LessRecord());
+ std::sort(ItinClassList.begin(), ItinClassList.end(), LessRecord());
// For each itinerary class
unsigned N = ItinClassList.size();
ItinClassesMap[Name] = i;
}
+ // Emit size of table
+ OS<<"\nenum {\n";
+ OS<<" ItinClassesSize = " << N << "\n";
+ OS<<"};\n";
+
// Return itinerary class count
return N;
}
std::string &ItinString,
unsigned &NStages) {
// Get states list
- std::vector<Record*> StageList = ItinData->getValueAsListDef("Stages");
+ std::vector<Record*> StageList = ItinData->getValueAsListOfDefs("Stages");
// For each stage
unsigned N = NStages = StageList.size();
- for (unsigned i = 0; i < N; i++) {
+ for (unsigned i = 0; i < N;) {
// Next stage
Record *Stage = StageList[i];
// Form string as ,{ cycles, u1 | u2 | ... | un }
int Cycles = Stage->getValueAsInt("Cycles");
- ItinString += " ,{ " + itostr(Cycles) + ", ";
+ ItinString += " { " + itostr(Cycles) + ", ";
// Get unit list
- std::vector<Record*> UnitList = Stage->getValueAsListDef("Units");
+ std::vector<Record*> UnitList = Stage->getValueAsListOfDefs("Units");
// For each unit
for (unsigned j = 0, M = UnitList.size(); j < M;) {
// Close off stage
ItinString += " }";
+ if (++i < N) ItinString += ", ";
}
}
// Begin stages table
OS << "static llvm::InstrStage Stages[] = {\n"
- " { 0, 0 } // No itinerary\n";
+ " { 0, 0 }, // No itinerary\n";
unsigned ItinEnum = 1;
std::map<std::string, unsigned> ItinMap;
ItinList.resize(NItinClasses);
// Get itinerary data list
- std::vector<Record*> ItinDataList = Proc->getValueAsListDef("IID");
+ std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
// For each itinerary data
for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) {
// If new itinerary
if (Find == 0) {
- // Emit as ,{ cycles, u1 | u2 | ... | un } // index
- OS << ItinString << " // " << ItinEnum << "\n";
+ // Emit as { cycles, u1 | u2 | ... | un }, // index
+ OS << ItinString << ", // " << ItinEnum << "\n";
+ // Record Itin class number
ItinMap[ItinString] = Find = ItinEnum++;
}
ProcList.push_back(ItinList);
}
+ // Closing stage
+ OS << " { 0, 0 } // End itinerary\n";
// End stages table
OS << "};\n";
+
+ // Emit size of table
+ OS<<"\nenum {\n";
+ OS<<" StagesSize = sizeof(Stages)/sizeof(llvm::InstrStage)\n";
+ OS<<"};\n";
}
//
-// EmitProcessData - Generate data for processor itineraries.
+// EmitProcessorData - Generate data for processor itineraries.
//
-void SubtargetEmitter::EmitProcessData(std::ostream &OS,
+void SubtargetEmitter::EmitProcessorData(std::ostream &OS,
std::vector<std::vector<InstrItinerary> > &ProcList) {
// Get an iterator for processor itinerary stages
std::vector<std::vector<InstrItinerary> >::iterator
// For each itinerary class
std::vector<InstrItinerary> &ItinList = *ProcListIter++;
- unsigned ItinIndex = 0;
for (unsigned j = 0, M = ItinList.size(); j < M;) {
InstrItinerary &Intinerary = ItinList[j];
}
}
+//
+// EmitProcessorLookup - generate cpu name to itinerary lookup table.
+//
+void SubtargetEmitter::EmitProcessorLookup(std::ostream &OS) {
+ // Gather and sort processor information
+ std::vector<Record*> ProcessorList =
+ Records.getAllDerivedDefinitions("Processor");
+ std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
+
+ // Begin processor table
+ OS << "\n";
+ OS << "// Sorted (by key) array of itineraries for CPU subtype.\n"
+ << "static const llvm::SubtargetInfoKV ProcItinKV[] = {\n";
+
+ // For each processor
+ for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
+ // Next processor
+ Record *Processor = ProcessorList[i];
+
+ std::string Name = Processor->getValueAsString("Name");
+ std::string ProcItin = Processor->getValueAsDef("ProcItin")->getName();
+
+ // Emit as { "cpu", procinit },
+ OS << " { "
+ << "\"" << Name << "\", "
+ << "(void *)&" << ProcItin;
+
+ OS << " }";
+
+ // Depending on ''if more in the list'' emit comma
+ if (++i < N) OS << ",";
+
+ OS << "\n";
+ }
+
+ // End processor table
+ OS << "};\n";
+
+ // Emit size of table
+ OS<<"\nenum {\n";
+ OS<<" ProcItinKVSize = sizeof(ProcItinKV)/"
+ "sizeof(llvm::SubtargetInfoKV)\n";
+ OS<<"};\n";
+}
+
//
// EmitData - Emits all stages and itineries, folding common patterns.
//
std::vector<std::vector<InstrItinerary> > ProcList;
// Enumerate all the itinerary classes
- unsigned NItinClasses = CollectAllItinClasses(ItinClassesMap);
- // Emit the stage data
- EmitStageData(OS, NItinClasses, ItinClassesMap, ProcList);
- // Emit the processor itinerary data
- EmitProcessData(OS, ProcList);
+ unsigned NItinClasses = CollectAllItinClasses(OS, ItinClassesMap);
+ // Make sure the rest is worth the effort
+ HasItineraries = NItinClasses != 1; // Ignore NoItinerary.
+
+ if (HasItineraries) {
+ // Emit the stage data
+ EmitStageData(OS, NItinClasses, ItinClassesMap, ProcList);
+ // Emit the processor itinerary data
+ EmitProcessorData(OS, ProcList);
+ // Emit the processor lookup data
+ EmitProcessorLookup(OS);
+ }
}
//
void SubtargetEmitter::ParseFeaturesFunction(std::ostream &OS) {
std::vector<Record*> Features =
Records.getAllDerivedDefinitions("SubtargetFeature");
- sort(Features.begin(), Features.end(), LessRecord());
+ std::sort(Features.begin(), Features.end(), LessRecord());
OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
"// subtarget options.\n"
Record *R = Features[i];
std::string Instance = R->getName();
std::string Name = R->getValueAsString("Name");
- std::string Type = R->getValueAsString("Type");
+ std::string Value = R->getValueAsString("Value");
std::string Attribute = R->getValueAsString("Attribute");
-
- OS << " " << Attribute << " = (Bits & " << Instance << ") != 0;\n";
+
+ OS << " if ((Bits & " << Instance << ") != 0) "
+ << Attribute << " = " << Value << ";\n";
}
+
+ if (HasItineraries) {
+ OS << "\n"
+ << " InstrItinerary *Itinerary = (InstrItinerary *)"
+ "Features.getInfo(ProcItinKV, ProcItinKVSize);\n"
+ " InstrItins = InstrItineraryData(Stages, Itinerary);\n";
+ }
+
OS << "}\n";
}
projects / oota-llvm.git / blobdiff