MC/AsmMatcher: Fix indirect 80-col viola.

[oota-llvm.git] / utils / TableGen / SubtargetEmitter.h

diff --git a/utils/TableGen/SubtargetEmitter.h b/utils/TableGen/SubtargetEmitter.h
index f1cc4982923ee847ec8c257b95ff7a4f41eca407..3abec3b24091186e896fed783993d6b420b31a4b 100644 (file)
--- a/utils/TableGen/SubtargetEmitter.h
+++ b/utils/TableGen/SubtargetEmitter.h
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by James M. Laskey and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -15,16 +15,49 @@
 #define SUBTARGET_EMITTER_H
 
 #include "TableGenBackend.h"
+#include "llvm/Target/TargetInstrItineraries.h"
+#include <vector>
+#include <map>
+#include <string>
+
 
 namespace llvm {
 
 class SubtargetEmitter : public TableGenBackend {
+  
   RecordKeeper &Records;
+  std::string Target;
+  bool HasItineraries;
+  
+  void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits);
+  void FeatureKeyValues(raw_ostream &OS);
+  void CPUKeyValues(raw_ostream &OS);
+  unsigned CollectAllItinClasses(raw_ostream &OS,
+                                 std::map<std::string,unsigned> &ItinClassesMap,
+                                 std::vector<Record*> &ItinClassList);
+  void FormItineraryStageString(const std::string &Names,
+                                Record *ItinData, std::string &ItinString,
+                                unsigned &NStages);
+  void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString,
+                                       unsigned &NOperandCycles);
+  void FormItineraryBypassString(const std::string &Names,
+                                 Record *ItinData,
+                                 std::string &ItinString, unsigned NOperandCycles);
+  void EmitStageAndOperandCycleData(raw_ostream &OS, unsigned NItinClasses,
+                     std::map<std::string, unsigned> &ItinClassesMap,
+                     std::vector<Record*> &ItinClassList,
+                     std::vector<std::vector<InstrItinerary> > &ProcList);
+  void EmitProcessorData(raw_ostream &OS,
+                       std::vector<std::vector<InstrItinerary> > &ProcList);
+  void EmitProcessorLookup(raw_ostream &OS);
+  void EmitData(raw_ostream &OS);
+  void ParseFeaturesFunction(raw_ostream &OS);
+  
 public:
-  SubtargetEmitter(RecordKeeper &R) : Records(R) {}
+  SubtargetEmitter(RecordKeeper &R) : Records(R), HasItineraries(false) {}
 
   // run - Output the subtarget enumerations, returning true on failure.
-  void run(std::ostream &o);
+  void run(raw_ostream &o);
 
 };