MC/AsmMatcher: Fix indirect 80-col viola.

[oota-llvm.git] / utils / TableGen / SubtargetEmitter.h

diff --git a/utils/TableGen/SubtargetEmitter.h b/utils/TableGen/SubtargetEmitter.h
index f882f1d53cfc53050f6d9b6fae217caaa71d57dc..3abec3b24091186e896fed783993d6b420b31a4b 100644 (file)
--- a/utils/TableGen/SubtargetEmitter.h
+++ b/utils/TableGen/SubtargetEmitter.h
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by James M. Laskey and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -27,28 +27,37 @@ class SubtargetEmitter : public TableGenBackend {
   
   RecordKeeper &Records;
   std::string Target;
+  bool HasItineraries;
   
-  void Enumeration(std::ostream &OS, const char *ClassName, bool isBits);
-  void FeatureKeyValues(std::ostream &OS);
-  void CPUKeyValues(std::ostream &OS);
-  unsigned CollectAllItinClasses(std::map<std::string, unsigned>
-                                                               &ItinClassesMap);
-  void FormItineraryString(Record *ItinData, std::string &ItinString,
-                           unsigned &NStages);
-  void EmitStageData(std::ostream &OS, unsigned NItinClasses,
+  void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits);
+  void FeatureKeyValues(raw_ostream &OS);
+  void CPUKeyValues(raw_ostream &OS);
+  unsigned CollectAllItinClasses(raw_ostream &OS,
+                                 std::map<std::string,unsigned> &ItinClassesMap,
+                                 std::vector<Record*> &ItinClassList);
+  void FormItineraryStageString(const std::string &Names,
+                                Record *ItinData, std::string &ItinString,
+                                unsigned &NStages);
+  void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString,
+                                       unsigned &NOperandCycles);
+  void FormItineraryBypassString(const std::string &Names,
+                                 Record *ItinData,
+                                 std::string &ItinString, unsigned NOperandCycles);
+  void EmitStageAndOperandCycleData(raw_ostream &OS, unsigned NItinClasses,
                      std::map<std::string, unsigned> &ItinClassesMap,
+                     std::vector<Record*> &ItinClassList,
                      std::vector<std::vector<InstrItinerary> > &ProcList);
-  void EmitProcessorData(std::ostream &OS,
+  void EmitProcessorData(raw_ostream &OS,
                        std::vector<std::vector<InstrItinerary> > &ProcList);
-  void EmitProcessorLookup(std::ostream &OS);
-  void EmitData(std::ostream &OS);
-  void ParseFeaturesFunction(std::ostream &OS);
+  void EmitProcessorLookup(raw_ostream &OS);
+  void EmitData(raw_ostream &OS);
+  void ParseFeaturesFunction(raw_ostream &OS);
   
 public:
-  SubtargetEmitter(RecordKeeper &R) : Records(R) {}
+  SubtargetEmitter(RecordKeeper &R) : Records(R), HasItineraries(false) {}
 
   // run - Output the subtarget enumerations, returning true on failure.
-  void run(std::ostream &o);
+  void run(raw_ostream &o);
 
 };