Generate cpu to itinerary map.

[oota-llvm.git] / utils / TableGen / SubtargetEmitter.h

diff --git a/utils/TableGen/SubtargetEmitter.h b/utils/TableGen/SubtargetEmitter.h
index 2a7b70be25de25d3257d975418fabebc34872f17..f882f1d53cfc53050f6d9b6fae217caaa71d57dc 100644 (file)
--- a/utils/TableGen/SubtargetEmitter.h
+++ b/utils/TableGen/SubtargetEmitter.h
@@ -23,13 +23,6 @@
 
 namespace llvm {
 
-//
-// Convenience types.
-//
-typedef std::map<std::string, unsigned> IntMap;
-typedef std::vector<InstrItinerary> IntineraryList;
-typedef std::vector<IntineraryList> ProcessorList;
-
 class SubtargetEmitter : public TableGenBackend {
   
   RecordKeeper &Records;
@@ -38,12 +31,16 @@ class SubtargetEmitter : public TableGenBackend {
   void Enumeration(std::ostream &OS, const char *ClassName, bool isBits);
   void FeatureKeyValues(std::ostream &OS);
   void CPUKeyValues(std::ostream &OS);
-  unsigned CollectAllItinClasses(IntMap &ItinClassesMap);
+  unsigned CollectAllItinClasses(std::map<std::string, unsigned>
+                                                               &ItinClassesMap);
   void FormItineraryString(Record *ItinData, std::string &ItinString,
-                           unsigned &N);
-  void EmitStageData(std::ostream &OS, unsigned N,
-                     IntMap &ItinClassesMap, ProcessorList &ProcList);
-  void EmitProcessData(std::ostream &OS, ProcessorList &ProcList);
+                           unsigned &NStages);
+  void EmitStageData(std::ostream &OS, unsigned NItinClasses,
+                     std::map<std::string, unsigned> &ItinClassesMap,
+                     std::vector<std::vector<InstrItinerary> > &ProcList);
+  void EmitProcessorData(std::ostream &OS,
+                       std::vector<std::vector<InstrItinerary> > &ProcList);
+  void EmitProcessorLookup(std::ostream &OS);
   void EmitData(std::ostream &OS);
   void ParseFeaturesFunction(std::ostream &OS);