Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step

[oota-llvm.git] / utils / TableGen / X86DisassemblerShared.h

diff --git a/utils/TableGen/X86DisassemblerShared.h b/utils/TableGen/X86DisassemblerShared.h
index 9003cbfbdee94b9db3a5d9a3ee77ad36a049a3a0..0417e9dece405fc7942777fa2ff7b00c8e2af019 100644 (file)
--- a/utils/TableGen/X86DisassemblerShared.h
+++ b/utils/TableGen/X86DisassemblerShared.h
@@ -11,19 +11,20 @@
 #define X86DISASSEMBLERSHARED_H
 
 #include <string>
+#include <string.h>
 
-#define INSTRUCTION_SPECIFIER_FIELDS    \
-  bool                    filtered;     \
-  InstructionContext      insnContext;  \
-  std::string             name;         \
-                                        \
-  InstructionSpecifier() {              \
-    filtered = false;                   \
-    insnContext = IC;                   \
-    name = "";                          \
-    modifierType = MODIFIER_NONE;       \
-    modifierBase = 0;                   \
-    bzero(operands, sizeof(operands));  \
+#define INSTRUCTION_SPECIFIER_FIELDS       \
+  bool                    filtered;        \
+  InstructionContext      insnContext;     \
+  std::string             name;            \
+                                           \
+  InstructionSpecifier() {                 \
+    filtered = false;                      \
+    insnContext = IC;                      \
+    name = "";                             \
+    modifierType = MODIFIER_NONE;          \
+    modifierBase = 0;                      \
+    memset(operands, 0, sizeof(operands)); \
   }
 
 #define INSTRUCTION_IDS           \