Revert "Disable LeakSanitizer in TableGen binaries, see PR18325"

[oota-llvm.git] / utils / TableGen / X86RecognizableInstr.h

diff --git a/utils/TableGen/X86RecognizableInstr.h b/utils/TableGen/X86RecognizableInstr.h
index 9ec36a39df4503af5dcac60a80146bbd760f4766..ef3bdfee254f336632fe323b3417440ce857dbad 100644 (file)
--- a/utils/TableGen/X86RecognizableInstr.h
+++ b/utils/TableGen/X86RecognizableInstr.h
@@ -44,8 +44,6 @@ private:
   uint8_t Opcode;
   /// The form field from the record
   uint8_t Form;
-  /// The segment override field from the record
-  uint8_t SegOvr;
   /// The hasOpSizePrefix field from the record
   bool HasOpSizePrefix;
   /// The hasAdSizePrefix field from the record
@@ -66,10 +64,22 @@ private:
   bool HasMemOp4Prefix;
   /// The ignoreVEX_L field from the record
   bool IgnoresVEX_L;
+  /// The hasEVEXPrefix field from the record
+  bool HasEVEXPrefix;
+  /// The hasEVEX_L2Prefix field from the record
+  bool HasEVEX_L2Prefix;
+  /// The hasEVEX_K field from the record
+  bool HasEVEX_K;
+  /// The hasEVEX_KZ field from the record
+  bool HasEVEX_KZ;
+  /// The hasEVEX_B field from the record
+  bool HasEVEX_B;
   /// The hasLockPrefix field from the record
   bool HasLockPrefix;
-  /// The isCodeGenOnly filed from the record
+  /// The isCodeGenOnly field from the record
   bool IsCodeGenOnly;
+  /// The ForceDisassemble field from the record
+  bool ForceDisassemble;
   // Whether the instruction has the predicate "In64BitMode"
   bool Is64Bit;
   // Whether the instruction has the predicate "In32BitMode"
@@ -82,9 +92,6 @@ private:
   
   /// Indicates whether the instruction is SSE
   bool IsSSE;
-  /// Indicates whether the instruction has FR operands - MOVs with FR operands
-  /// are typically ignored
-  bool HasFROperands;
   /// Indicates whether the instruction should be emitted into the decode
   /// tables; regardless, it will be emitted into the instruction info table
   bool ShouldBeEmitted;
@@ -176,6 +183,8 @@ private:
                                                           bool hasOpSizePrefix);
   static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
                                                         bool HasOpSizePrefix);
+  static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s,
+                                                             bool HasOpSizePrefix);
   
   /// handleOperand - Converts a single operand from the LLVM table format to
   ///   the emitted table format, handling any duplicate operands it encounters
@@ -220,9 +229,7 @@ private:
   /// emitInstructionSpecifier - Loads the instruction specifier for the current
   ///   instruction into a DisassemblerTables.
   ///
-  /// \param tables The DisassemblerTables to populate with the specifier for
-  ///               the current instruction.
-  void emitInstructionSpecifier(DisassemblerTables &tables);
+  void emitInstructionSpecifier();
   
   /// emitDecodePath - Populates the proper fields in the decode tables
   ///   corresponding to the decode paths for this instruction.