#ifndef X86RECOGNIZABLEINSTR_H
#define X86RECOGNIZABLEINSTR_H
-#include "X86DisassemblerTables.h"
-
#include "CodeGenTarget.h"
-#include "Record.h"
-
-#include "llvm/Support/DataTypes.h"
+#include "X86DisassemblerTables.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/Support/DataTypes.h"
+#include "llvm/TableGen/Record.h"
namespace llvm {
uint8_t Opcode;
/// The form field from the record
uint8_t Form;
- /// The segment override field from the record
- uint8_t SegOvr;
/// The hasOpSizePrefix field from the record
bool HasOpSizePrefix;
+ /// The hasAdSizePrefix field from the record
+ bool HasAdSizePrefix;
/// The hasREX_WPrefix field from the record
bool HasREX_WPrefix;
/// The hasVEXPrefix field from the record
bool HasVEXPrefix;
/// The hasVEX_4VPrefix field from the record
bool HasVEX_4VPrefix;
+ /// The hasVEX_4VOp3Prefix field from the record
+ bool HasVEX_4VOp3Prefix;
/// The hasVEX_WPrefix field from the record
bool HasVEX_WPrefix;
/// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
bool HasVEX_LPrefix;
+ /// The hasMemOp4Prefix field from the record
+ bool HasMemOp4Prefix;
+ /// The ignoreVEX_L field from the record
+ bool IgnoresVEX_L;
+ /// The hasEVEXPrefix field from the record
+ bool HasEVEXPrefix;
+ /// The hasEVEX_L2Prefix field from the record
+ bool HasEVEX_L2Prefix;
+ /// The hasEVEX_K field from the record
+ bool HasEVEX_K;
+ /// The hasEVEX_KZ field from the record
+ bool HasEVEX_KZ;
+ /// The hasEVEX_B field from the record
+ bool HasEVEX_B;
/// The hasLockPrefix field from the record
bool HasLockPrefix;
- /// The isCodeGenOnly filed from the record
+ /// The isCodeGenOnly field from the record
bool IsCodeGenOnly;
-
+ /// The ForceDisassemble field from the record
+ bool ForceDisassemble;
+ // Whether the instruction has the predicate "In64BitMode"
+ bool Is64Bit;
+ // Whether the instruction has the predicate "In32BitMode"
+ bool Is32Bit;
+
/// The instruction name as listed in the tables
std::string Name;
/// The AT&T AsmString for the instruction
/// Indicates whether the instruction is SSE
bool IsSSE;
- /// Indicates whether the instruction has FR operands - MOVs with FR operands
- /// are typically ignored
- bool HasFROperands;
/// Indicates whether the instruction should be emitted into the decode
/// tables; regardless, it will be emitted into the instruction info table
bool ShouldBeEmitted;
/// hasFROperands - Returns true if any operand is a FR operand.
bool hasFROperands() const;
-
- /// has256BitOperands - Returns true if any operand is a 256-bit SSE operand.
- bool has256BitOperands() const;
-
+
/// typeFromString - Translates an operand type from the string provided in
/// the LLVM tables to an OperandType for use in the operand specifier.
///
/// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
/// prefix. If it does, 32-bit register operands stay
/// 32-bit regardless of the operand size.
- /// @param hasOpSizePrefix- Indicates whether the instruction has an OpSize
+ /// @param hasOpSizePrefix Indicates whether the instruction has an OpSize
/// prefix. If it does not, then 16-bit register
/// operands stay 16-bit.
/// @return - The operand's type.
bool hasOpSizePrefix);
static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
bool HasOpSizePrefix);
+ static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s,
+ bool HasOpSizePrefix);
/// handleOperand - Converts a single operand from the LLVM table format to
/// the emitted table format, handling any duplicate operands it encounters
unsigned &operandIndex,
unsigned &physicalOperandIndex,
unsigned &numPhysicalOperands,
- unsigned *operandMapping,
+ const unsigned *operandMapping,
OperandEncoding (*encodingFromString)
(const std::string&,
bool hasOpSizePrefix));
/// emitInstructionSpecifier - Loads the instruction specifier for the current
/// instruction into a DisassemblerTables.
///
- /// @arg tables - The DisassemblerTables to populate with the specifier for
- /// the current instruction.
- void emitInstructionSpecifier(DisassemblerTables &tables);
+ void emitInstructionSpecifier();
/// emitDecodePath - Populates the proper fields in the decode tables
/// corresponding to the decode paths for this instruction.
///
- /// @arg tables - The DisassemblerTables to populate with the decode
+ /// \param tables The DisassemblerTables to populate with the decode
/// decode information for the current instruction.
void emitDecodePath(DisassemblerTables &tables) const;
/// Constructor - Initializes a RecognizableInstr with the appropriate fields
/// from a CodeGenInstruction.
///
- /// @arg tables - The DisassemblerTables that the specifier will be added to.
- /// @arg insn - The CodeGenInstruction to extract information from.
- /// @arg uid - The unique ID of the current instruction.
+ /// \param tables The DisassemblerTables that the specifier will be added to.
+ /// \param insn The CodeGenInstruction to extract information from.
+ /// \param uid The unique ID of the current instruction.
RecognizableInstr(DisassemblerTables &tables,
const CodeGenInstruction &insn,
InstrUID uid);
/// processInstr - Accepts a CodeGenInstruction and loads decode information
/// for it into a DisassemblerTables if appropriate.
///
- /// @arg tables - The DiassemblerTables to be populated with decode
+ /// \param tables The DiassemblerTables to be populated with decode
/// information.
- /// @arg insn - The CodeGenInstruction to be used as a source for this
+ /// \param insn The CodeGenInstruction to be used as a source for this
/// information.
- /// @uid - The unique ID of the instruction.
+ /// \param uid The unique ID of the instruction.
static void processInstr(DisassemblerTables &tables,
const CodeGenInstruction &insn,
InstrUID uid);
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