X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;ds=inline;f=utils%2FTableGen%2FAsmWriterEmitter.cpp;h=4b543d3f9fc65b49c09ad38bf650b24df7cc6460;hb=47f0e3f434e2e43f951c3a826c40906cb15b7285;hp=4089ede9cfee1506eeabcedfeb77e81b53b8929b;hpb=170c95ff7666573c2c011a8f1a84b51a6ea9e1fc;p=oota-llvm.git diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp index 4089ede9cfe..4b543d3f9fc 100644 --- a/utils/TableGen/AsmWriterEmitter.cpp +++ b/utils/TableGen/AsmWriterEmitter.cpp @@ -208,9 +208,6 @@ FindUniqueOperandCommands(std::vector &UniqueOperandCommands, // Otherwise, scan to see if all of the other instructions in this command // set share the operand. bool AllSame = true; - // Keep track of the maximum, number of operands or any - // instruction we see in the group. - size_t MaxSize = FirstInst->Operands.size(); for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx); NIT != InstIdxs.end(); @@ -220,10 +217,6 @@ FindUniqueOperandCommands(std::vector &UniqueOperandCommands, const AsmWriterInst *OtherInst = getAsmWriterInstByID(NIT-InstIdxs.begin()); - if (OtherInst && - OtherInst->Operands.size() > FirstInst->Operands.size()) - MaxSize = std::max(MaxSize, OtherInst->Operands.size()); - if (!OtherInst || OtherInst->Operands.size() == Op || OtherInst->Operands[Op] != FirstInst->Operands[Op]) { AllSame = false; @@ -285,12 +278,15 @@ static void UnescapeString(std::string &Str) { void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { Record *AsmWriter = Target.getAsmWriter(); std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); + unsigned PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); O << "/// printInstruction - This method is automatically generated by tablegen\n" "/// from the instruction set description.\n" "void " << Target.getName() << ClassName - << "::printInstruction(const MCInst *MI, raw_ostream &O) {\n"; + << "::printInstruction(const MCInst *MI, " + << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "") + << "raw_ostream &O) {\n"; // Build an aggregate string, and build a table of offsets into it. SequenceToOffsetTable StringTable; @@ -350,7 +346,7 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { // in the opcode-indexed table. unsigned BitsLeft = 64-AsmStrBits; - std::vector > TableDrivenOperandPrinters; + std::vector> TableDrivenOperandPrinters; while (1) { std::vector UniqueOperandCommands; @@ -393,7 +389,7 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { } // Remember the handlers for this set of operands. - TableDrivenOperandPrinters.push_back(UniqueOperandCommands); + TableDrivenOperandPrinters.push_back(std::move(UniqueOperandCommands)); } @@ -531,12 +527,12 @@ static const char *getMinimalTypeForRange(uint64_t Range) { static void emitRegisterNameString(raw_ostream &O, StringRef AltName, - const std::vector &Registers) { + const std::deque &Registers) { SequenceToOffsetTable StringTable; SmallVector AsmNames(Registers.size()); - for (unsigned i = 0, e = Registers.size(); i != e; ++i) { - const CodeGenRegister &Reg = *Registers[i]; - std::string &AsmName = AsmNames[i]; + unsigned i = 0; + for (const auto &Reg : Registers) { + std::string &AsmName = AsmNames[i++]; // "NoRegAltName" is special. We don't need to do a lookup for that, // as it's just a reference to the default register name. @@ -587,8 +583,7 @@ emitRegisterNameString(raw_ostream &O, StringRef AltName, void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { Record *AsmWriter = Target.getAsmWriter(); std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); - const std::vector &Registers = - Target.getRegBank().getRegisters(); + const auto &Registers = Target.getRegBank().getRegisters(); std::vector AltNameIndices = Target.getRegAltNameIndices(); bool hasAltNames = AltNameIndices.size() > 1; @@ -663,20 +658,26 @@ public: std::pair parseName(StringRef::iterator Start, StringRef::iterator End) { StringRef::iterator I = Start; + StringRef::iterator Next; if (*I == '{') { // ${some_name} Start = ++I; while (I != End && *I != '}') ++I; + Next = I; + // eat the final '}' + if (Next != End) + ++Next; } else { // $name, just eat the usual suspects. while (I != End && ((*I >= 'a' && *I <= 'z') || (*I >= 'A' && *I <= 'Z') || (*I >= '0' && *I <= '9') || *I == '_')) ++I; + Next = I; } - return std::make_pair(StringRef(Start, I - Start), I); + return std::make_pair(StringRef(Start, I - Start), Next); } void print(raw_ostream &O) { @@ -726,23 +727,21 @@ public: ++I; } } - OS.flush(); // Emit the string. - O.indent(6) << "AsmString = \"" << OutString.str() << "\";\n"; + O.indent(6) << "AsmString = \"" << OutString << "\";\n"; O.indent(6) << "break;\n"; O.indent(4) << '}'; } - bool operator==(const IAPrinter &RHS) { + bool operator==(const IAPrinter &RHS) const { if (Conds.size() != RHS.Conds.size()) return false; unsigned Idx = 0; - for (std::vector::iterator - I = Conds.begin(), E = Conds.end(); I != E; ++I) - if (*I != RHS.Conds[Idx++]) + for (const auto &str : Conds) + if (str != RHS.Conds[Idx++]) return false; return true; @@ -761,12 +760,12 @@ static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) { namespace { struct AliasPriorityComparator { - typedef std::pair ValueType; + typedef std::pair ValueType; bool operator()(const ValueType &LHS, const ValueType &RHS) { if (LHS.second == RHS.second) { // We don't actually care about the order, but for consistency it // shouldn't depend on pointer comparisons. - return LHS.first->TheDef->getName() < RHS.first->TheDef->getName(); + return LHS.first.TheDef->getName() < RHS.first.TheDef->getName(); } // Aliases with larger priorities should be considered first. @@ -789,17 +788,17 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { // Emit the method that prints the alias instruction. std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); unsigned Variant = AsmWriter->getValueAsInt("Variant"); + unsigned PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); std::vector AllInstAliases = Records.getAllDerivedDefinitions("InstAlias"); // Create a map from the qualified name to a list of potential matches. - typedef std::set, AliasPriorityComparator> + typedef std::set, AliasPriorityComparator> AliasWithPriority; std::map AliasMap; for (std::vector::iterator I = AllInstAliases.begin(), E = AllInstAliases.end(); I != E; ++I) { - CodeGenInstAlias *Alias = new CodeGenInstAlias(*I, Variant, Target); const Record *R = *I; int Priority = R->getValueAsInt("EmitPriority"); if (Priority < 1) @@ -807,13 +806,13 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { const DagInit *DI = R->getValueAsDag("ResultInst"); const DefInit *Op = cast(DI->getOperator()); - AliasMap[getQualifiedName(Op->getDef())].insert(std::make_pair(Alias, - Priority)); + AliasMap[getQualifiedName(Op->getDef())].insert( + std::make_pair(CodeGenInstAlias(*I, Variant, Target), Priority)); } // A map of which conditions need to be met for each instruction operand // before it can be matched to the mnemonic. - std::map > IAPrinterMap; + std::map> IAPrinterMap; // A list of MCOperandPredicates for all operands in use, and the reverse map std::vector MCOpPredicates; @@ -821,25 +820,24 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { for (auto &Aliases : AliasMap) { for (auto &Alias : Aliases.second) { - const CodeGenInstAlias *CGA = Alias.first; - unsigned LastOpNo = CGA->ResultInstOperandIndex.size(); + const CodeGenInstAlias &CGA = Alias.first; + unsigned LastOpNo = CGA.ResultInstOperandIndex.size(); unsigned NumResultOps = - CountNumOperands(CGA->ResultInst->AsmString, Variant); + CountNumOperands(CGA.ResultInst->AsmString, Variant); // Don't emit the alias if it has more operands than what it's aliasing. - if (NumResultOps < CountNumOperands(CGA->AsmString, Variant)) + if (NumResultOps < CountNumOperands(CGA.AsmString, Variant)) continue; - IAPrinter *IAP = new IAPrinter(CGA->Result->getAsString(), - CGA->AsmString); + IAPrinter IAP(CGA.Result->getAsString(), CGA.AsmString); unsigned NumMIOps = 0; - for (auto &Operand : CGA->ResultOperands) + for (auto &Operand : CGA.ResultOperands) NumMIOps += Operand.getMINumOperands(); std::string Cond; Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(NumMIOps); - IAP->addCond(Cond); + IAP.addCond(Cond); bool CantHandle = false; @@ -847,7 +845,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { for (unsigned i = 0, e = LastOpNo; i != e; ++i) { std::string Op = "MI->getOperand(" + llvm::utostr(MIOpNum) + ")"; - const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i]; + const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i]; switch (RO.Kind) { case CodeGenInstAlias::ResultOperand::K_Record: { @@ -873,11 +871,11 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { if (Rec->isSubClassOf("RegisterOperand")) Rec = Rec->getValueAsDef("RegClass"); if (Rec->isSubClassOf("RegisterClass")) { - IAP->addCond(Op + ".isReg()"); + IAP.addCond(Op + ".isReg()"); - if (!IAP->isOpMapped(ROName)) { - IAP->addOperand(ROName, MIOpNum, PrintMethodIdx); - Record *R = CGA->ResultOperands[i].getRecord(); + if (!IAP.isOpMapped(ROName)) { + IAP.addOperand(ROName, MIOpNum, PrintMethodIdx); + Record *R = CGA.ResultOperands[i].getRecord(); if (R->isSubClassOf("RegisterOperand")) R = R->getValueAsDef("RegClass"); Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" + @@ -885,12 +883,12 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { ".contains(" + Op + ".getReg())"; } else { Cond = Op + ".getReg() == MI->getOperand(" + - llvm::utostr(IAP->getOpIndex(ROName)) + ").getReg()"; + llvm::utostr(IAP.getOpIndex(ROName)) + ").getReg()"; } } else { // Assume all printable operands are desired for now. This can be // overridden in the InstAlias instantiation if necessary. - IAP->addOperand(ROName, MIOpNum, PrintMethodIdx); + IAP.addOperand(ROName, MIOpNum, PrintMethodIdx); // There might be an additional predicate on the MCOperand unsigned Entry = MCOpPredicateMap[Rec]; @@ -906,39 +904,38 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { Op + ", " + llvm::utostr(Entry) + ")"; } // for all subcases of ResultOperand::K_Record: - IAP->addCond(Cond); + IAP.addCond(Cond); break; } case CodeGenInstAlias::ResultOperand::K_Imm: { // Just because the alias has an immediate result, doesn't mean the // MCInst will. An MCExpr could be present, for example. - IAP->addCond(Op + ".isImm()"); + IAP.addCond(Op + ".isImm()"); - Cond = Op + ".getImm() == " - + llvm::utostr(CGA->ResultOperands[i].getImm()); - IAP->addCond(Cond); + Cond = Op + ".getImm() == " + + llvm::utostr(CGA.ResultOperands[i].getImm()); + IAP.addCond(Cond); break; } case CodeGenInstAlias::ResultOperand::K_Reg: // If this is zero_reg, something's playing tricks we're not // equipped to handle. - if (!CGA->ResultOperands[i].getRegister()) { + if (!CGA.ResultOperands[i].getRegister()) { CantHandle = true; break; } - Cond = Op + ".getReg() == " + Target.getName() + - "::" + CGA->ResultOperands[i].getRegister()->getName(); - IAP->addCond(Cond); + Cond = Op + ".getReg() == " + Target.getName() + "::" + + CGA.ResultOperands[i].getRegister()->getName(); + IAP.addCond(Cond); break; } - if (!IAP) break; MIOpNum += RO.getMINumOperands(); } if (CantHandle) continue; - IAPrinterMap[Aliases.first].push_back(IAP); + IAPrinterMap[Aliases.first].push_back(std::move(IAP)); } } @@ -951,35 +948,32 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { HeaderO << "bool " << Target.getName() << ClassName << "::printAliasInstr(const MCInst" - << " *MI, raw_ostream &OS) {\n"; + << " *MI, " << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "") + << "raw_ostream &OS) {\n"; std::string Cases; raw_string_ostream CasesO(Cases); - for (std::map >::iterator - I = IAPrinterMap.begin(), E = IAPrinterMap.end(); I != E; ++I) { - std::vector &IAPs = I->second; + for (auto &Entry : IAPrinterMap) { + std::vector &IAPs = Entry.second; std::vector UniqueIAPs; - for (std::vector::iterator - II = IAPs.begin(), IE = IAPs.end(); II != IE; ++II) { - IAPrinter *LHS = *II; + for (auto &LHS : IAPs) { bool IsDup = false; - for (std::vector::iterator - III = IAPs.begin(), IIE = IAPs.end(); III != IIE; ++III) { - IAPrinter *RHS = *III; - if (LHS != RHS && *LHS == *RHS) { + for (const auto &RHS : IAPs) { + if (&LHS != &RHS && LHS == RHS) { IsDup = true; break; } } - if (!IsDup) UniqueIAPs.push_back(LHS); + if (!IsDup) + UniqueIAPs.push_back(&LHS); } if (UniqueIAPs.empty()) continue; - CasesO.indent(2) << "case " << I->first << ":\n"; + CasesO.indent(2) << "case " << Entry.first << ":\n"; for (std::vector::iterator II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) { @@ -1000,7 +994,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { return; } - if (MCOpPredicates.size()) + if (!MCOpPredicates.empty()) O << "static bool " << Target.getName() << ClassName << "ValidateMCOperand(\n" << " const MCOperand &MCOp, unsigned PredicateIndex);\n"; @@ -1029,9 +1023,13 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { O << " ++I;\n"; O << " int OpIdx = AsmString[I++] - 1;\n"; O << " int PrintMethodIdx = AsmString[I++] - 1;\n"; - O << " printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);\n"; + O << " printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, "; + O << (PassSubtarget ? "STI, " : ""); + O << "OS);\n"; O << " } else\n"; - O << " printOperand(MI, unsigned(AsmString[I++]) - 1, OS);\n"; + O << " printOperand(MI, unsigned(AsmString[I++]) - 1, "; + O << (PassSubtarget ? "STI, " : ""); + O << "OS);\n"; O << " } else {\n"; O << " OS << AsmString[I++];\n"; O << " }\n"; @@ -1048,7 +1046,9 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { O << "void " << Target.getName() << ClassName << "::" << "printCustomAliasOperand(\n" << " const MCInst *MI, unsigned OpIdx,\n" - << " unsigned PrintMethodIdx, raw_ostream &OS) {\n"; + << " unsigned PrintMethodIdx,\n" + << (PassSubtarget ? " const MCSubtargetInfo &STI,\n" : "") + << " raw_ostream &OS) {\n"; if (PrintMethods.empty()) O << " llvm_unreachable(\"Unknown PrintMethod kind\");\n"; else { @@ -1059,14 +1059,15 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { for (unsigned i = 0; i < PrintMethods.size(); ++i) { O << " case " << i << ":\n" - << " " << PrintMethods[i] << "(MI, OpIdx, OS);\n" + << " " << PrintMethods[i] << "(MI, OpIdx, " + << (PassSubtarget ? "STI, " : "") << "OS);\n" << " break;\n"; } O << " }\n"; } O << "}\n\n"; - if (MCOpPredicates.size()) { + if (!MCOpPredicates.empty()) { O << "static bool " << Target.getName() << ClassName << "ValidateMCOperand(\n" << " const MCOperand &MCOp, unsigned PredicateIndex) {\n" @@ -1093,13 +1094,10 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) { Record *AsmWriter = Target.getAsmWriter(); - for (CodeGenTarget::inst_iterator I = Target.inst_begin(), - E = Target.inst_end(); - I != E; ++I) - if (!(*I)->AsmString.empty() && (*I)->TheDef->getName() != "PHI") - Instructions.push_back( - AsmWriterInst(**I, AsmWriter->getValueAsInt("Variant"), - AsmWriter->getValueAsInt("OperandSpacing"))); + for (const CodeGenInstruction *I : Target.instructions()) + if (!I->AsmString.empty() && I->TheDef->getName() != "PHI") + Instructions.emplace_back(*I, AsmWriter->getValueAsInt("Variant"), + AsmWriter->getValueAsInt("PassSubtarget")); // Get the instruction numbering. NumberedInstructions = &Target.getInstructionsByEnumValue();