X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;ds=sidebyside;f=lib%2FCodeGen%2FRegisterClassInfo.cpp;h=786d279c2b8c29e0a09a011d49b72fe7fa74a783;hb=08f5cdf5b33b8202edddb24abee6af2a0b3ae49c;hp=84e62d2c02543ef727d97e88ea52465c0b412376;hpb=d365fa9415ce31b5f0a6019b33c6f099a82f4e34;p=oota-llvm.git

diff --git a/lib/CodeGen/RegisterClassInfo.cpp b/lib/CodeGen/RegisterClassInfo.cpp
index 84e62d2c025..786d279c2b8 100644
--- a/lib/CodeGen/RegisterClassInfo.cpp
+++ b/lib/CodeGen/RegisterClassInfo.cpp
@@ -77,40 +77,38 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
     RCI.Order.reset(new unsigned[NumRegs]);
 
   unsigned N = 0;
-  SmallVector<std::pair<unsigned, unsigned>, 8> CSRAlias;
+  SmallVector<unsigned, 16> CSRAlias;
 
   // FIXME: Once targets reserve registers instead of removing them from the
   // allocation order, we can simply use begin/end here.
-  TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF);
-  TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF);
-
-  for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
-    unsigned PhysReg = *I;
+  ArrayRef<unsigned> RawOrder = RC->getRawAllocationOrder(*MF);
+  for (unsigned i = 0; i != RawOrder.size(); ++i) {
+    unsigned PhysReg = RawOrder[i];
     // Remove reserved registers from the allocation order.
     if (Reserved.test(PhysReg))
       continue;
-    if (unsigned CSR = CSRNum[PhysReg])
-      // PhysReg aliases a CSR, save it for later.  Provide a (CSR, N) sort key
-      // to preserve the original ordering of multiple aliases of the same CSR.
-      CSRAlias.push_back(std::make_pair((CSR << 16) + (I - AOB), PhysReg));
+    if (CSRNum[PhysReg])
+      // PhysReg aliases a CSR, save it for later.
+      CSRAlias.push_back(PhysReg);
     else
       RCI.Order[N++] = PhysReg;
   }
   RCI.NumRegs = N + CSRAlias.size();
   assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
 
-  // Sort CSR aliases acording to the CSR ordering.
-  if (CSRAlias.size() >= 2)
-    array_pod_sort(CSRAlias.begin(), CSRAlias.end());
+  // CSR aliases go after the volatile registers, preserve the target's order.
+  std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]);
 
-  for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i)
-      RCI.Order[N++] = CSRAlias[i].second;
+  // Check if RC is a proper sub-class.
+  if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
+    if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
+      RCI.ProperSubClass = true;
 
   DEBUG({
     dbgs() << "AllocationOrder(" << RC->getName() << ") = [";
-    for (unsigned I = 0; I != N; ++I)
+    for (unsigned I = 0; I != RCI.NumRegs; ++I)
       dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
-    dbgs() << " ]\n";
+    dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
   });
 
   // RCI is now up-to-date.