X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;ds=sidebyside;f=lib%2FTarget%2FSparc%2FFPMover.cpp;h=9a729bd8704458ddeee395a1170ec3a1d4f49be5;hb=fef904d0e824a2c587f8c1063b6c4fbf47fec898;hp=70f203ccca919bf16022d006a4eab88e91f19f12;hpb=7c90f73a1b06040d971a3dd95a491031ae6238d5;p=oota-llvm.git diff --git a/lib/Target/Sparc/FPMover.cpp b/lib/Target/Sparc/FPMover.cpp index 70f203ccca9..9a729bd8704 100644 --- a/lib/Target/Sparc/FPMover.cpp +++ b/lib/Target/Sparc/FPMover.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -11,27 +11,32 @@ // //===----------------------------------------------------------------------===// +#define DEBUG_TYPE "fpmover" #include "Sparc.h" #include "SparcSubtarget.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetInstrInfo.h" #include "llvm/ADT/Statistic.h" #include "llvm/Support/Debug.h" -#include +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; -namespace { - Statistic<> NumFpDs("fpmover", "Number of instructions translated"); - Statistic<> NoopFpDs("fpmover", "Number of noop instructions removed"); +STATISTIC(NumFpDs , "Number of instructions translated"); +STATISTIC(NoopFpDs, "Number of noop instructions removed"); +namespace { struct FPMover : public MachineFunctionPass { /// Target machine description which we query for reg. names, data /// layout, etc. /// TargetMachine &TM; - - FPMover(TargetMachine &tm) : TM(tm) { } + + static char ID; + explicit FPMover(TargetMachine &tm) + : MachineFunctionPass(ID), TM(tm) { } virtual const char *getPassName() const { return "Sparc Double-FP Move Fixer"; @@ -40,6 +45,7 @@ namespace { bool runOnMachineBasicBlock(MachineBasicBlock &MBB); bool runOnMachineFunction(MachineFunction &F); }; + char FPMover::ID = 0; } // end of anonymous namespace /// createSparcFPMoverPass - Returns a pass that turns FpMOVD @@ -53,25 +59,25 @@ FunctionPass *llvm::createSparcFPMoverPass(TargetMachine &tm) { /// registers that correspond to it. static void getDoubleRegPair(unsigned DoubleReg, unsigned &EvenReg, unsigned &OddReg) { - static const unsigned EvenHalvesOfPairs[] = { + static const uint16_t EvenHalvesOfPairs[] = { SP::F0, SP::F2, SP::F4, SP::F6, SP::F8, SP::F10, SP::F12, SP::F14, SP::F16, SP::F18, SP::F20, SP::F22, SP::F24, SP::F26, SP::F28, SP::F30 }; - static const unsigned OddHalvesOfPairs[] = { + static const uint16_t OddHalvesOfPairs[] = { SP::F1, SP::F3, SP::F5, SP::F7, SP::F9, SP::F11, SP::F13, SP::F15, SP::F17, SP::F19, SP::F21, SP::F23, SP::F25, SP::F27, SP::F29, SP::F31 }; - static const unsigned DoubleRegsInOrder[] = { + static const uint16_t DoubleRegsInOrder[] = { SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15 }; - for (unsigned i = 0; i < sizeof(DoubleRegsInOrder)/sizeof(unsigned); ++i) + for (unsigned i = 0; i < array_lengthof(DoubleRegsInOrder); ++i) if (DoubleRegsInOrder[i] == DoubleReg) { EvenReg = EvenHalvesOfPairs[i]; OddReg = OddHalvesOfPairs[i]; return; } - assert(0 && "Can't find reg"); + llvm_unreachable("Can't find reg"); } /// runOnMachineBasicBlock - Fixup FpMOVD instructions in this MBB. @@ -80,6 +86,7 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) { bool Changed = false; for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) { MachineInstr *MI = I++; + DebugLoc dl = MI->getDebugLoc(); if (MI->getOpcode() == SP::FpMOVD || MI->getOpcode() == SP::FpABSD || MI->getOpcode() == SP::FpNEGD) { Changed = true; @@ -95,22 +102,24 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) { getDoubleRegPair(DestDReg, EvenDestReg, OddDestReg); getDoubleRegPair(SrcDReg, EvenSrcReg, OddSrcReg); + const TargetInstrInfo *TII = TM.getInstrInfo(); if (MI->getOpcode() == SP::FpMOVD) - MI->setOpcode(SP::FMOVS); + MI->setDesc(TII->get(SP::FMOVS)); else if (MI->getOpcode() == SP::FpNEGD) - MI->setOpcode(SP::FNEGS); + MI->setDesc(TII->get(SP::FNEGS)); else if (MI->getOpcode() == SP::FpABSD) - MI->setOpcode(SP::FABSS); + MI->setDesc(TII->get(SP::FABSS)); else - assert(0 && "Unknown opcode!"); + llvm_unreachable("Unknown opcode!"); - MI->SetMachineOperandReg(0, EvenDestReg); - MI->SetMachineOperandReg(1, EvenSrcReg); - DEBUG(std::cerr << "FPMover: the modified instr is: " << *MI); + MI->getOperand(0).setReg(EvenDestReg); + MI->getOperand(1).setReg(EvenSrcReg); + DEBUG(errs() << "FPMover: the modified instr is: " << *MI); // Insert copy for the other half of the double. if (DestDReg != SrcDReg) { - MI = BuildMI(MBB, I, SP::FMOVS, 1, OddDestReg).addReg(OddSrcReg); - DEBUG(std::cerr << "FPMover: the inserted instr is: " << *MI); + MI = BuildMI(MBB, I, dl, TM.getInstrInfo()->get(SP::FMOVS), OddDestReg) + .addReg(OddSrcReg); + DEBUG(errs() << "FPMover: the inserted instr is: " << *MI); } ++NumFpDs; }