X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;ds=sidebyside;f=utils%2FTableGen%2FCodeEmitterGen.cpp;h=7e6c769ac4f52dd102c04a508fbf977584cbcd5d;hb=9e6d1d1f5034347d237941f1bf08fba5c1583cd3;hp=f0a02872cebe0b386e3f85154d1d0b95e90f79d3;hpb=cb129031479dfb5583cce6d77fcbb0b68098693a;p=oota-llvm.git

diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp
index f0a02872ceb..7e6c769ac4f 100644
--- a/utils/TableGen/CodeEmitterGen.cpp
+++ b/utils/TableGen/CodeEmitterGen.cpp
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -24,8 +24,18 @@ void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
   for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
        I != E; ++I) {
     Record *R = *I;
-    if (R->getName() == "PHI" || R->getName() == "INLINEASM") continue;
-    
+    if (R->getName() == "PHI" ||
+        R->getName() == "INLINEASM" ||
+        R->getName() == "DBG_LABEL" ||
+        R->getName() == "EH_LABEL" ||
+        R->getName() == "GC_LABEL" ||
+        R->getName() == "KILL" ||
+        R->getName() == "EXTRACT_SUBREG" ||
+        R->getName() == "INSERT_SUBREG" ||
+        R->getName() == "IMPLICIT_DEF" ||
+        R->getName() == "SUBREG_TO_REG" ||
+        R->getName() == "COPY_TO_REGCLASS") continue;
+
     BitsInit *BI = R->getValueAsBitsInit("Inst");
 
     unsigned numBits = BI->getNumBits();
@@ -65,7 +75,7 @@ int CodeEmitterGen::getVariableBit(const std::string &VarName,
 } 
 
 
-void CodeEmitterGen::run(std::ostream &o) {
+void CodeEmitterGen::run(raw_ostream &o) {
   CodeGenTarget Target;
   std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
   
@@ -80,7 +90,7 @@ void CodeEmitterGen::run(std::ostream &o) {
 
   // Emit function declaration
   o << "unsigned " << Target.getName() << "CodeEmitter::"
-    << "getBinaryCodeForInstr(MachineInstr &MI) {\n";
+    << "getBinaryCodeForInstr(const MachineInstr &MI) {\n";
 
   // Emit instruction base values
   o << "  static const unsigned InstBits[] = {\n";
@@ -91,27 +101,33 @@ void CodeEmitterGen::run(std::ostream &o) {
     const CodeGenInstruction *CGI = *IN;
     Record *R = CGI->TheDef;
     
-    if (IN != NumberedInstructions.begin()) o << ",\n";
-    
-    if (R->getName() == "PHI" || R->getName() == "INLINEASM") {
-      o << "    0U";
+    if (R->getName() == "PHI" ||
+        R->getName() == "INLINEASM" ||
+        R->getName() == "DBG_LABEL" ||
+        R->getName() == "EH_LABEL" ||
+        R->getName() == "GC_LABEL" ||
+        R->getName() == "KILL" ||
+        R->getName() == "EXTRACT_SUBREG" ||
+        R->getName() == "INSERT_SUBREG" ||
+        R->getName() == "IMPLICIT_DEF" ||
+        R->getName() == "SUBREG_TO_REG" ||
+        R->getName() == "COPY_TO_REGCLASS") {
+      o << "    0U,\n";
       continue;
     }
     
     BitsInit *BI = R->getValueAsBitsInit("Inst");
 
-    unsigned Value = 0;
-    const std::vector<RecordVal> &Vals = R->getValues();
-
     // Start by filling in fixed values...
+    unsigned Value = 0;
     for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
       if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1))) {
         Value |= B->getValue() << (e-i-1);
       }
     }
-    o << "    " << Value << "U";
+    o << "    " << Value << "U," << '\t' << "// " << R->getName() << "\n";
   }
-  o << "\n  };\n";
+  o << "    0U\n  };\n";
   
   // Map to accumulate all the cases.
   std::map<std::string, std::vector<std::string> > CaseMap;
@@ -123,11 +139,22 @@ void CodeEmitterGen::run(std::ostream &o) {
     const std::string &InstName = R->getName();
     std::string Case("");
     
-    if (InstName == "PHI" || InstName == "INLINEASM") continue;
-    
+    if (InstName == "PHI" ||
+        InstName == "INLINEASM" ||
+        InstName == "DBG_LABEL"||
+        InstName == "EH_LABEL"||
+        InstName == "GC_LABEL"||
+        InstName == "KILL"||
+        InstName == "EXTRACT_SUBREG" ||
+        InstName == "INSERT_SUBREG" ||
+        InstName == "IMPLICIT_DEF" ||
+        InstName == "SUBREG_TO_REG" ||
+        InstName == "COPY_TO_REGCLASS") continue;
+
     BitsInit *BI = R->getValueAsBitsInit("Inst");
     const std::vector<RecordVal> &Vals = R->getValues();
-
+    CodeGenInstruction &CGI = Target.getInstruction(InstName);
+    
     // Loop over all of the fields in the instruction, determining which are the
     // operands to the instruction.
     unsigned op = 0;
@@ -156,14 +183,18 @@ void CodeEmitterGen::run(std::ostream &o) {
             }
 
             if (!gotOp) {
+              /// If this operand is not supposed to be emitted by the generated
+              /// emitter, skip it.
+              while (CGI.isFlatOperandNotEmitted(op))
+                ++op;
+              
               Case += "      // op: " + VarName + "\n"
                    +  "      op = getMachineOpValue(MI, MI.getOperand("
-                   +  utostr(op++)
-                   +  "));\n";
+                   +  utostr(op++) + "));\n";
               gotOp = true;
             }
             
-            unsigned opMask = (1 << N) - 1;
+            unsigned opMask = ~0U >> (32-N);
             int opShift = beginVarBit - N + 1;
             opMask <<= opShift;
             opShift = beginInstBit - beginVarBit;
@@ -182,7 +213,7 @@ void CodeEmitterGen::run(std::ostream &o) {
       }
     }
 
-    std::vector<std::string> &InstList =  CaseMap[Case];
+    std::vector<std::string> &InstList = CaseMap[Case];
     InstList.push_back(InstName);
   }
 
@@ -190,7 +221,8 @@ void CodeEmitterGen::run(std::ostream &o) {
   // Emit initial function code
   o << "  const unsigned opcode = MI.getOpcode();\n"
     << "  unsigned Value = InstBits[opcode];\n"
-    << "  unsigned op;\n"
+    << "  unsigned op = 0;\n"
+    << "  op = op;  // suppress warning\n"
     << "  switch (opcode) {\n";
 
   // Emit each case statement
@@ -211,8 +243,10 @@ void CodeEmitterGen::run(std::ostream &o) {
 
   // Default case: unhandled opcode
   o << "  default:\n"
-    << "    std::cerr << \"Not supported instr: \" << MI << \"\\n\";\n"
-    << "    abort();\n"
+    << "    std::string msg;\n"
+    << "    raw_string_ostream Msg(msg);\n"
+    << "    Msg << \"Not supported instr: \" << MI;\n"
+    << "    llvm_report_error(Msg.str());\n"
     << "  }\n"
     << "  return Value;\n"
     << "}\n\n";