X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;ds=sidebyside;f=utils%2FTableGen%2FCodeGenSchedule.cpp;h=4cf7b5fbb50caf9b7d208ea63d67bf6c115e4d87;hb=da08412bd068ba21ad898f79ab1d05d1e9a9c14e;hp=6da3ad720265b5dce4402af05dda07983a6615f5;hpb=354362524a72b3fa43a6c09380b7ae3b2380cbba;p=oota-llvm.git diff --git a/utils/TableGen/CodeGenSchedule.cpp b/utils/TableGen/CodeGenSchedule.cpp index 6da3ad72026..4cf7b5fbb50 100644 --- a/utils/TableGen/CodeGenSchedule.cpp +++ b/utils/TableGen/CodeGenSchedule.cpp @@ -7,13 +7,11 @@ // //===----------------------------------------------------------------------===// // -// This file defines structures to encapsulate the machine model as decribed in +// This file defines structures to encapsulate the machine model as described in // the target description. // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "subtarget-emitter" - #include "CodeGenSchedule.h" #include "CodeGenTarget.h" #include "llvm/ADT/STLExtras.h" @@ -23,6 +21,8 @@ using namespace llvm; +#define DEBUG_TYPE "subtarget-emitter" + #ifndef NDEBUG static void dumpIdxVec(const IdxVec &V) { for (unsigned i = 0, e = V.size(); i < e; ++i) { @@ -36,18 +36,15 @@ static void dumpIdxVec(const SmallVectorImpl &V) { } #endif +namespace { // (instrs a, b, ...) Evaluate and union all arguments. Identical to AddOp. struct InstrsOp : public SetTheory::Operator { - virtual void apply(SetTheory &ST, DagInit *Expr, SetTheory::RecSet &Elts, - ArrayRef Loc); + void apply(SetTheory &ST, DagInit *Expr, SetTheory::RecSet &Elts, + ArrayRef Loc) override { + ST.evaluate(Expr->arg_begin(), Expr->arg_end(), Elts, Loc); + } }; -// Provide out-of-line definition to prevent weak vtable. -void InstrsOp::apply(SetTheory &ST, DagInit *Expr, SetTheory::RecSet &Elts, - ArrayRef Loc) { - ST.evaluate(Expr->arg_begin(), Expr->arg_end(), Elts, Loc); -} - // (instregex "OpcPat",...) Find all instructions matching an opcode pattern. // // TODO: Since this is a prefix match, perform a binary search over the @@ -60,38 +57,33 @@ struct InstRegexOp : public SetTheory::Operator { const CodeGenTarget &Target; InstRegexOp(const CodeGenTarget &t): Target(t) {} - virtual void apply(SetTheory &ST, DagInit *Expr, SetTheory::RecSet &Elts, - ArrayRef Loc); -}; - -// Provide out-of-line definition to prevent weak vtable. -void InstRegexOp::apply(SetTheory &ST, DagInit *Expr, SetTheory::RecSet &Elts, - ArrayRef Loc) { - SmallVector RegexList; - for (DagInit::const_arg_iterator - AI = Expr->arg_begin(), AE = Expr->arg_end(); AI != AE; ++AI) { - StringInit *SI = dyn_cast(*AI); - if (!SI) - PrintFatalError(Loc, "instregex requires pattern string: " - + Expr->getAsString()); - std::string pat = SI->getValue(); - // Implement a python-style prefix match. - if (pat[0] != '^') { - pat.insert(0, "^("); - pat.insert(pat.end(), ')'); - } - RegexList.push_back(new Regex(pat)); - } - for (CodeGenTarget::inst_iterator I = Target.inst_begin(), - E = Target.inst_end(); I != E; ++I) { - for (SmallVectorImpl::iterator - RI = RegexList.begin(), RE = RegexList.end(); RI != RE; ++RI) { - if ((*RI)->match((*I)->TheDef->getName())) - Elts.insert((*I)->TheDef); + void apply(SetTheory &ST, DagInit *Expr, SetTheory::RecSet &Elts, + ArrayRef Loc) override { + SmallVector RegexList; + for (DagInit::const_arg_iterator + AI = Expr->arg_begin(), AE = Expr->arg_end(); AI != AE; ++AI) { + StringInit *SI = dyn_cast(*AI); + if (!SI) + PrintFatalError(Loc, "instregex requires pattern string: " + + Expr->getAsString()); + std::string pat = SI->getValue(); + // Implement a python-style prefix match. + if (pat[0] != '^') { + pat.insert(0, "^("); + pat.insert(pat.end(), ')'); + } + RegexList.push_back(Regex(pat)); + } + for (CodeGenTarget::inst_iterator I = Target.inst_begin(), + E = Target.inst_end(); I != E; ++I) { + for (auto &R : RegexList) { + if (R.match((*I)->TheDef->getName())) + Elts.insert((*I)->TheDef); + } } } - DeleteContainerPointers(RegexList); -} +}; +} // end anonymous namespace /// CodeGenModels ctor interprets machine model records and populates maps. CodeGenSchedModels::CodeGenSchedModels(RecordKeeper &RK, @@ -190,7 +182,7 @@ void CodeGenSchedModels::addProcModel(Record *ProcDef) { // Recursively find all reachable SchedReadWrite records. static void scanSchedRW(Record *RWDef, RecVec &RWDefs, SmallPtrSet &RWSet) { - if (!RWSet.insert(RWDef)) + if (!RWSet.insert(RWDef).second) return; RWDefs.push_back(RWDef); // Reads don't current have sequence records, but it can be added later. @@ -435,7 +427,7 @@ void CodeGenSchedModels::expandRWSeqForProc( const CodeGenProcModel &ProcModel) const { const CodeGenSchedRW &SchedWrite = getSchedRW(RWIdx, IsRead); - Record *AliasDef = 0; + Record *AliasDef = nullptr; for (RecIter AI = SchedWrite.Aliases.begin(), AE = SchedWrite.Aliases.end(); AI != AE; ++AI) { const CodeGenSchedRW &AliasRW = getSchedRW((*AI)->getValueAsDef("AliasRW")); @@ -759,7 +751,7 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) { for (ArrayRef::const_iterator II = InstDefs.begin(), IE = InstDefs.end(); II != IE; ++II) { unsigned OldSCIdx = InstrClassMap[*II]; - if (OldSCIdx && RemappedClassIDs.insert(OldSCIdx)) { + if (OldSCIdx && RemappedClassIDs.insert(OldSCIdx).second) { for (RecIter RI = SchedClasses[OldSCIdx].InstRWs.begin(), RE = SchedClasses[OldSCIdx].InstRWs.end(); RI != RE; ++RI) { if ((*RI)->getValueAsDef("SchedModel") == RWModelDef) { @@ -1321,7 +1313,7 @@ static void inferFromTransitions(ArrayRef LastTransitions, IdxVec ProcIndices(I->ProcIndices.begin(), I->ProcIndices.end()); CodeGenSchedTransition SCTrans; SCTrans.ToClassIdx = - SchedModels.addSchedClass(/*ItinClassDef=*/0, OperWritesVariant, + SchedModels.addSchedClass(/*ItinClassDef=*/nullptr, OperWritesVariant, OperReadsVariant, ProcIndices); SCTrans.ProcIndices = ProcIndices; // The final PredTerm is unique set of predicates guarding the transition. @@ -1479,11 +1471,23 @@ void CodeGenSchedModels::collectProcResources() { Record *ModelDef = (*WRI)->getValueAsDef("SchedModel"); addWriteRes(*WRI, getProcModel(ModelDef).Index); } + RecVec SWRDefs = Records.getAllDerivedDefinitions("SchedWriteRes"); + for (RecIter WRI = SWRDefs.begin(), WRE = SWRDefs.end(); WRI != WRE; ++WRI) { + Record *ModelDef = (*WRI)->getValueAsDef("SchedModel"); + addWriteRes(*WRI, getProcModel(ModelDef).Index); + } RecVec RADefs = Records.getAllDerivedDefinitions("ReadAdvance"); for (RecIter RAI = RADefs.begin(), RAE = RADefs.end(); RAI != RAE; ++RAI) { Record *ModelDef = (*RAI)->getValueAsDef("SchedModel"); addReadAdvance(*RAI, getProcModel(ModelDef).Index); } + RecVec SRADefs = Records.getAllDerivedDefinitions("SchedReadAdvance"); + for (RecIter RAI = SRADefs.begin(), RAE = SRADefs.end(); RAI != RAE; ++RAI) { + if ((*RAI)->getValueInit("SchedModel")->isComplete()) { + Record *ModelDef = (*RAI)->getValueAsDef("SchedModel"); + addReadAdvance(*RAI, getProcModel(ModelDef).Index); + } + } // Add ProcResGroups that are defined within this processor model, which may // not be directly referenced but may directly specify a buffer size. RecVec ProcResGroups = Records.getAllDerivedDefinitions("ProcResGroup"); @@ -1615,7 +1619,7 @@ Record *CodeGenSchedModels::findProcResUnits(Record *ProcResKind, if (ProcResKind->isSubClassOf("ProcResourceUnits")) return ProcResKind; - Record *ProcUnitDef = 0; + Record *ProcUnitDef = nullptr; RecVec ProcResourceDefs = Records.getAllDerivedDefinitions("ProcResourceUnits");