X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=arch%2Farm%2Fboot%2Fdts%2Frk3288.dtsi;h=09c67c9f5d5e73ebc43a3623c45334fdf37e5be2;hb=d83da99f31f323d6699aeaf1b730ed93dd92d3d8;hp=63defd201de3fbc89db06e39b27abb8d17de14c3;hpb=7bc7cbf91c5c7b22949712b6d56fcd219fd6c080;p=firefly-linux-kernel-4.4.55.git diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 63defd201de3..09c67c9f5d5e 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -45,6 +45,7 @@ #include #include #include +#include #include "skeleton.dtsi" / { @@ -53,6 +54,7 @@ interrupt-parent = <&gic>; aliases { + ethernet0 = &gmac; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -203,15 +205,6 @@ #clock-cells = <0>; }; - edp_phy: edp-phy { - compatible = "rockchip,rk3288-dp-phy"; - clocks = <&cru SCLK_EDP_24M>; - clock-names = "24m"; - rockchip,grf = <&grf>; - #phy-cells = <0>; - status = "disabled"; - }; - timer { compatible = "arm,armv7-timer"; arm,cpu-registers-not-fw-configured; @@ -291,6 +284,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; }; @@ -457,7 +452,78 @@ }; thermal-zones { - #include "rk3288-thermal.dtsi" + reserve_thermal: reserve_thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; + }; + + cpu_thermal: cpu_thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT 6>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu_thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 2>; + + trips { + gpu_alert0: gpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_crit: gpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; }; tsadc: tsadc@ff280000 { @@ -480,8 +546,9 @@ gmac: ethernet@ff290000 { compatible = "rockchip,rk3288-gmac"; reg = <0xff290000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; rockchip,grf = <&grf>; clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, @@ -493,6 +560,7 @@ "aclk_mac", "pclk_mac"; resets = <&cru SRST_MAC>; reset-names = "stmmaceth"; + max-speed = <100>; status = "disabled"; }; @@ -635,6 +703,76 @@ reg = <0xff720000 0x1000>; }; + qos_gpu_r: qos@ffaa0000 { + compatible = "syscon"; + reg = <0xffaa0000 0x20>; + }; + + qos_gpu_w: qos@ffaa0080 { + compatible = "syscon"; + reg = <0xffaa0080 0x20>; + }; + + qos_vio1_vop: qos@ffad0000 { + compatible = "syscon"; + reg = <0xffad0000 0x20>; + }; + + qos_vio1_isp_w0: qos@ffad0100 { + compatible = "syscon"; + reg = <0xffad0100 0x20>; + }; + + qos_vio1_isp_w1: qos@ffad0180 { + compatible = "syscon"; + reg = <0xffad0180 0x20>; + }; + + qos_vio0_vop: qos@ffad0400 { + compatible = "syscon"; + reg = <0xffad0400 0x20>; + }; + + qos_vio0_vip: qos@ffad0480 { + compatible = "syscon"; + reg = <0xffad0480 0x20>; + }; + + qos_vio0_iep: qos@ffad0500 { + compatible = "syscon"; + reg = <0xffad0500 0x20>; + }; + + qos_vio2_rga_r: qos@ffad0800 { + compatible = "syscon"; + reg = <0xffad0800 0x20>; + }; + + qos_vio2_rga_w: qos@ffad0880 { + compatible = "syscon"; + reg = <0xffad0880 0x20>; + }; + + qos_vio1_isp_r: qos@ffad0900 { + compatible = "syscon"; + reg = <0xffad0900 0x20>; + }; + + qos_video: qos@ffae0000 { + compatible = "syscon"; + reg = <0xffae0000 0x20>; + }; + + qos_hevc_r: qos@ffaf0000 { + compatible = "syscon"; + reg = <0xffaf0000 0x20>; + }; + + qos_hevc_w: qos@ffaf0080 { + compatible = "syscon"; + reg = <0xffaf0080 0x20>; + }; + pmu: power-management@ff730000 { compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; reg = <0xff730000 0x100>; @@ -668,7 +806,7 @@ * *_HDMI HDMI * *_MIPI_* MIPI */ - pd_vio { + pd_vio@RK3288_PD_VIO { reg = ; clocks = <&cru ACLK_IEP>, <&cru ACLK_ISP>, @@ -695,17 +833,28 @@ <&cru SCLK_ISP_JPE>, <&cru SCLK_ISP>, <&cru SCLK_RGA>; + pm_qos = <&qos_vio0_iep>, + <&qos_vio1_vop>, + <&qos_vio1_isp_w0>, + <&qos_vio1_isp_w1>, + <&qos_vio0_vop>, + <&qos_vio0_vip>, + <&qos_vio2_rga_r>, + <&qos_vio2_rga_w>, + <&qos_vio1_isp_r>; }; /* * Note: The following 3 are HEVC(H.265) clocks, * and on the ACLK_HEVC_NIU (NOC). */ - pd_hevc { + pd_hevc@RK3288_PD_HEVC { reg = ; clocks = <&cru ACLK_HEVC>, <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>; + pm_qos = <&qos_hevc_r>, + <&qos_hevc_w>; }; /* @@ -713,21 +862,34 @@ * (video endecoder & decoder) clocks that on the * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). */ - pd_video { + pd_video@RK3288_PD_VIDEO { reg = ; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + pm_qos = <&qos_video>; }; /* * Note: ACLK_GPU is the GPU clock, * and on the ACLK_GPU_NIU (NOC). */ - pd_gpu { + pd_gpu@RK3288_PD_GPU { reg = ; clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu_r>, + <&qos_gpu_w>; }; }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x94>; + mode-normal = ; + mode-recovery = ; + mode-bootloader = ; + mode-loader = ; + mode-ums = ; + }; }; sgrf: syscon@ff740000 { @@ -757,8 +919,56 @@ }; grf: syscon@ff770000 { - compatible = "rockchip,rk3288-grf", "syscon"; + compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; reg = <0xff770000 0x1000>; + + edp_phy: edp-phy { + compatible = "rockchip,rk3288-dp-phy"; + clocks = <&cru SCLK_EDP_24M>; + clock-names = "24m"; + #phy-cells = <0>; + status = "disabled"; + }; + + io_domains: io-domains { + compatible = "rockchip,rk3288-io-voltage-domain"; + status = "disabled"; + }; + + usbphy: usbphy { + compatible = "rockchip,rk3288-usb-phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy@320 { + #phy-cells = <0>; + reg = <0x320>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + resets = <&cru SRST_USBOTG_PHY>; + reset-names = "phy-reset"; + }; + + usbphy1: usb-phy@334 { + #phy-cells = <0>; + reg = <0x334>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; + }; + + usbphy2: usb-phy@348 { + #phy-cells = <0>; + reg = <0x348>; + clocks = <&cru SCLK_OTGPHY2>; + clock-names = "phyclk"; + #clock-cells = <0>; + resets = <&cru SRST_USBHOST1_PHY>; + reset-names = "phy-reset"; + }; + }; }; wdt: watchdog@ff800000 { @@ -796,6 +1006,22 @@ clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <2>; + status = "disabled"; + }; + + rga: rga@ff920000 { + compatible = "rockchip,rk3288-rga"; + reg = <0xff920000 0x180>; + interrupts = ; + interrupt-names = "rga"; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; + clock-names = "aclk", "hclk", "sclk"; + + resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; + + reset-names = "core", "axi", "ahb"; status = "disabled"; }; @@ -902,16 +1128,13 @@ interrupts = ; clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; clock-names = "ref", "pclk"; + power-domains = <&power RK3288_PD_VIO>; rockchip,grf = <&grf>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; ports { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - mipi_in: port { #address-cells = <1>; #size-cells = <0>; @@ -1060,6 +1283,26 @@ status = "disabled"; }; + vpu_service: vpu-service@ff9a0000 { + compatible = "rockchip,vpu_service"; + reg = <0xff9a0000 0x800>; + interrupts = , + ; + interrupt-names = "irq_enc", "irq_dec"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + power-domains = <&power RK3288_PD_VIDEO>; + rockchip,grf = <&grf>; + resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>; + reset-names = "video_a", "video_h"; + iommus = <&vpu_mmu>; + iommu_enabled = <1>; + dev_mode = <0>; + status = "disabled"; + /* 0 means ion, 1 means drm */ + allocator = <1>; + }; + vpu_mmu: iommu@ff9a0800 { compatible = "rockchip,iommu"; reg = <0xff9a0800 0x100>; @@ -1069,6 +1312,47 @@ #iommu-cells = <0>; }; + hevc_service: hevc-service@ff9c0000 { + compatible = "rockchip,hevc_service"; + reg = <0xff9c0000 0x400>; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, + <&cru SCLK_HEVC_CORE>, + <&cru SCLK_HEVC_CABAC>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", + "clk_cabac"; + /* + * The 4K hevc would also work well with 500/125/300/300, + * no more err irq and reset request. + */ + assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, + <&cru SCLK_HEVC_CORE>, + <&cru SCLK_HEVC_CABAC>; + assigned-clock-rates = <400000000>, <100000000>, + <300000000>, <300000000>; + + resets = <&cru SRST_HEVC>; + reset-names = "video"; + power-domains = <&power RK3288_PD_HEVC>; + rockchip,grf = <&grf>; + dev_mode = <1>; + iommus = <&hevc_mmu>; + iommu_enabled = <1>; + status = "disabled"; + /* 0 means ion, 1 means drm */ + allocator = <1>; + }; + + hevc_mmu: iommu@ff9c0440 { + compatible = "rockchip,iommu"; + reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>; + interrupts = ; + interrupt-names = "hevc_mmu"; + power-domains = <&power RK3288_PD_HEVC>; + #iommu-cells = <0>; + }; + gic: interrupt-controller@ffc01000 { compatible = "arm,gic-400"; interrupt-controller; @@ -1095,33 +1379,24 @@ }; }; - usbphy: phy { - compatible = "rockchip,rk3288-usb-phy"; + cif_isp0: cif_isp@ff910000 { + compatible = "rockchip,rk3288-cif-isp"; rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; + reg = <0xff910000 0x10000>, <0xff968000 0x4000>; + reg-names = "register", "csihost-register"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, + <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>, + <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>, + <&cru SCLK_MIPIDSI_24M>; + clock-names = "aclk_isp", "hclk_isp", + "sclk_isp", "sclk_isp_jpe", + "pclk_mipi_csi", "pclk_isp_in", + "sclk_mipidsi_24m"; + resets = <&cru SRST_ISP>; + reset-names = "rst_isp"; + interrupts = ; + interrupt-names = "cif_isp10_irq"; status = "disabled"; - - usbphy0: usb-phy0 { - #phy-cells = <0>; - reg = <0x320>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - }; - - usbphy1: usb-phy1 { - #phy-cells = <0>; - reg = <0x334>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - }; - - usbphy2: usb-phy2 { - #phy-cells = <0>; - reg = <0x348>; - clocks = <&cru SCLK_OTGPHY2>; - clock-names = "phyclk"; - }; }; pinctrl: pinctrl { @@ -1692,5 +1967,21 @@ rockchip,pins = ; }; }; + + cif { + cif_dvp_d2d9: cif-dvp-d2d9 { + rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>, + <2 1 RK_FUNC_1 &pcfg_pull_none>, + <2 2 RK_FUNC_1 &pcfg_pull_none>, + <2 3 RK_FUNC_1 &pcfg_pull_none>, + <2 4 RK_FUNC_1 &pcfg_pull_none>, + <2 5 RK_FUNC_1 &pcfg_pull_none>, + <2 6 RK_FUNC_1 &pcfg_pull_none>, + <2 7 RK_FUNC_1 &pcfg_pull_none>, + <2 8 RK_FUNC_1 &pcfg_pull_none>, + <2 9 RK_FUNC_1 &pcfg_pull_none>, + <2 11 RK_FUNC_1 &pcfg_pull_none>; + }; + }; }; };