X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=arch%2Farm%2Fboot%2Fdts%2Frk3288.dtsi;h=99bce3b994eb663f8bca946699162e574fc2b36f;hb=aba4c4996d4f675dcf00b0d74185c4fd32405580;hp=04ea209f1737f9fb052f4efc8589e98aa027836e;hpb=ff6e0fd55ef24e62efe5c9ab8327312164554250;p=firefly-linux-kernel-4.4.55.git diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 04ea209f1737..99bce3b994eb 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -45,6 +45,7 @@ #include #include #include +#include #include "skeleton.dtsi" / { @@ -144,6 +145,8 @@ interrupts = , ; #dma-cells = <1>; + arm,pl330-broken-no-flushp; + peripherals-req-type-burst; clocks = <&cru ACLK_DMAC2>; clock-names = "apb_pclk"; }; @@ -154,6 +157,8 @@ interrupts = , ; #dma-cells = <1>; + arm,pl330-broken-no-flushp; + peripherals-req-type-burst; clocks = <&cru ACLK_DMAC1>; clock-names = "apb_pclk"; status = "disabled"; @@ -165,6 +170,8 @@ interrupts = , ; #dma-cells = <1>; + arm,pl330-broken-no-flushp; + peripherals-req-type-burst; clocks = <&cru ACLK_DMAC1>; clock-names = "apb_pclk"; }; @@ -197,6 +204,15 @@ #clock-cells = <0>; }; + edp_phy: edp-phy { + compatible = "rockchip,rk3288-dp-phy"; + clocks = <&cru SCLK_EDP_24M>; + clock-names = "24m"; + rockchip,grf = <&grf>; + #phy-cells = <0>; + status = "disabled"; + }; + timer { compatible = "arm,armv7-timer"; arm,cpu-registers-not-fw-configured; @@ -266,6 +282,7 @@ interrupts = ; reg = <0xff0f0000 0x4000>; status = "disabled"; + supports-emmc; }; saradc: saradc@ff100000 { @@ -477,6 +494,7 @@ "aclk_mac", "pclk_mac"; resets = <&cru SRST_MAC>; reset-names = "stmmaceth"; + max-speed = <100>; status = "disabled"; }; @@ -712,6 +730,16 @@ clocks = <&cru ACLK_GPU>; }; }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x94>; + mode-normal = ; + mode-recovery = ; + mode-bootloader = ; + mode-loader = ; + mode-ums = ; + }; }; sgrf: syscon@ff740000 { @@ -725,16 +753,19 @@ rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru PLL_NPLL>, <&cru ACLK_CPU>, - <&cru HCLK_CPU>, <&cru PCLK_CPU>, - <&cru ACLK_PERI>, <&cru HCLK_PERI>, - <&cru PCLK_PERI>; - assigned-clock-rates = <594000000>, <400000000>, + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, <&cru ACLK_CPU>, + <&cru HCLK_CPU>, <&cru PCLK_CPU>, + <&cru ACLK_PERI>, <&cru HCLK_PERI>, + <&cru PCLK_PERI>; + assigned-clock-rates = <0>, <0>, + <594000000>, <400000000>, <500000000>, <300000000>, <150000000>, <75000000>, <300000000>, <150000000>, <75000000>; + assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>; }; grf: syscon@ff770000 { @@ -758,7 +789,7 @@ clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; dmas = <&dmac_bus_s 3>; dma-names = "tx"; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&spdif_tx>; rockchip,grf = <&grf>; @@ -768,7 +799,7 @@ i2s: i2s@ff890000 { compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; reg = <0xff890000 0x10000>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; @@ -800,6 +831,21 @@ reg = <0>; remote-endpoint = <&hdmi_in_vopb>; }; + + vopb_out_edp: endpoint@1 { + reg = <1>; + remote-endpoint = <&edp_in_vopb>; + }; + + vopb_out_mipi: endpoint@2 { + reg = <2>; + remote-endpoint = <&mipi_in_vopb>; + }; + + vopb_out_lvds: endpoint@3 { + reg = <3>; + remote-endpoint = <&lvds_in_vopb>; + }; }; }; @@ -833,6 +879,22 @@ reg = <0>; remote-endpoint = <&hdmi_in_vopl>; }; + + vopl_out_edp: endpoint@1 { + reg = <1>; + remote-endpoint = <&edp_in_vopl>; + }; + + vopl_out_mipi: endpoint@2 { + reg = <2>; + remote-endpoint = <&mipi_in_vopl>; + }; + + vopl_out_lvds: endpoint@3 { + reg = <3>; + remote-endpoint = <&lvds_in_vopl>; + }; + }; }; @@ -846,6 +908,102 @@ status = "disabled"; }; + mipi_dsi: mipi@ff960000 { + compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0xff960000 0x4000>; + interrupts = ; + clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; + clock-names = "ref", "pclk"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_in: port { + #address-cells = <1>; + #size-cells = <0>; + mipi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_mipi>; + }; + mipi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_mipi>; + }; + }; + }; + }; + + edp: dp@ff970000 { + compatible = "rockchip,rk3288-dp"; + reg = <0xff970000 0x4000>; + interrupts = ; + clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; + clock-names = "dp", "pclk"; + phys = <&edp_phy>; + phy-names = "dp"; + resets = <&cru SRST_EDP>; + reset-names = "dp"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + edp_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + edp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_edp>; + }; + edp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_edp>; + }; + }; + }; + }; + + lvds: lvds@ff96c000 { + compatible = "rockchip,rk3288-lvds"; + reg = <0xff96c000 0x4000>; + clocks = <&cru PCLK_LVDS_PHY>; + clock-names = "pclk_lvds"; + pinctrl-names = "default"; + pinctrl-0 = <&lcdc0_ctl>; + power-domains = <&power RK3288_PD_VIO>; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + lvds_in: port@0 { + reg = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + lvds_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_lvds>; + }; + lvds_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_lvds>; + }; + }; + }; + }; + hdmi: hdmi@ff980000 { compatible = "rockchip,rk3288-dw-hdmi"; reg = <0xff980000 0x20000>; @@ -873,6 +1031,74 @@ }; }; + gpu: gpu@ffa30000 { + compatible = "arm,malit764", + "arm,malit76x", + "arm,malit7xx", + "arm,mali-midgard"; + reg = <0xffa30000 0x10000>; + interrupts = , + , + ; + interrupt-names = "JOB", "MMU", "GPU"; + clocks = <&cru ACLK_GPU>; + clock-names = "clk_mali"; + operating-points = < + /* KHz uV */ + 600000 1250000 + /* 500000 1200000 - See crosbug.com/p/33857 */ + 400000 1100000 + 300000 1000000 + 200000 950000 + 100000 950000 + >; + #cooling-cells = <2>; /* min followed by max */ + power-domains = <&power RK3288_PD_GPU>; + status = "disabled"; + }; + + vpu: video-codec@ff9a0000 { + compatible = "rockchip,rk3288-vpu"; + reg = <0xff9a0000 0x800>; + interrupts = , + ; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3288_PD_VIDEO>; + iommus = <&vpu_mmu>; + assigned-clocks = <&cru ACLK_VCODEC>; + assigned-clock-rates = <400000000>; + status = "disabled"; + }; + + vpu_service: vpu-service@ff9a0000 { + compatible = "rockchip,vpu_service"; + reg = <0xff9a0000 0x800>; + interrupts = , + ; + interrupt-names = "irq_enc", "irq_dec"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + power-domains = <&power RK3288_PD_VIDEO>; + rockchip,grf = <&grf>; + resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>; + reset-names = "video_a", "video_h"; + iommus = <&vpu_mmu>; + iommu_enabled = <1>; + dev_mode = <0>; + status = "disabled"; + }; + + vpu_mmu: iommu@ff9a0800 { + compatible = "rockchip,iommu"; + reg = <0xff9a0800 0x100>; + interrupts = ; + interrupt-names = "vpu_mmu"; + power-domains = <&power RK3288_PD_VIDEO>; + #iommu-cells = <0>; + }; + gic: interrupt-controller@ffc01000 { compatible = "arm,gic-400"; interrupt-controller; @@ -886,6 +1112,19 @@ interrupts = ; }; + efuse: efuse@ffb40000 { + compatible = "rockchip,rockchip-efuse"; + reg = <0xffb40000 0x20>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE256>; + clock-names = "pclk_efuse"; + + cpu_leakage: cpu_leakage@17 { + reg = <0x17 0x1>; + }; + }; + usbphy: phy { compatible = "rockchip,rk3288-usb-phy"; rockchip,grf = <&grf>; @@ -1082,6 +1321,12 @@ }; }; + edp { + edp_hpd: edp-hpd { + rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>; + }; + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, @@ -1135,6 +1380,15 @@ }; }; + lcdc0 { + lcdc0_ctl: lcdc0-ctl { + rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>, + <1 25 RK_FUNC_1 &pcfg_pull_none>, + <1 26 RK_FUNC_1 &pcfg_pull_none>, + <1 27 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + sdmmc { sdmmc_clk: sdmmc-clk { rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;