X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=arch%2Farm%2Fmach-rk2928%2Fpm.c;h=2c95c023ef9bb0ffff2851be3bb61cd6e417eb71;hb=ca5addfee896d8feeece49a0a84cbdd09f2657f9;hp=76002182c41f5dd5ece6e636136313a8cbb0dde4;hpb=fd3316fde02fdeab8b36fcd60cad6a4a840421bc;p=firefly-linux-kernel-4.4.55.git

diff --git a/arch/arm/mach-rk2928/pm.c b/arch/arm/mach-rk2928/pm.c
old mode 100755
new mode 100644
index 76002182c41f..2c95c023ef9b
--- a/arch/arm/mach-rk2928/pm.c
+++ b/arch/arm/mach-rk2928/pm.c
@@ -196,21 +196,22 @@ static noinline void rk2928_pm_dump_inten(void)
 
 static void pm_pll_wait_lock(int pll_idx)
 {
-	u32 pll_state[4] = { 1, 0, 2, 3 };
+	u32 pll_state[4] = {1, 0, 2, 3};
 	u32 bit = 0x10u << pll_state[pll_idx];
-	u32 delay = pll_idx == APLL_ID ? 24000000U : 2400000000U;
+	int delay = 24000000;
 	while (delay > 0) {
-		if (grf_readl(GRF_SOC_STATUS0) & bit)
+		if ((cru_readl(PLL_CONS(pll_idx, 1)) & (0x1 << PLL_LOCK_SHIFT))) {
 			break;
+		}
 		delay--;
 	}
 	if (delay == 0) {
-		//CRU_PRINTK_ERR("wait pll bit 0x%x time out!\n", bit);
 		sram_printch('p');
 		sram_printch('l');
 		sram_printch('l');
 		sram_printhex(pll_idx);
 		sram_printch('\n');
+		while(1);
 	}
 }
 
@@ -218,6 +219,21 @@ static void pm_pll_wait_lock(int pll_idx)
 	cru_writel(PLL_PWR_DN_W_MSK|PLL_PWR_ON,PLL_CONS((id),3));\
 	pm_pll_wait_lock((id))
 
+static int pm_pll_pwr_up(u8 pll_id)
+{
+	u32 pllcon0,pllcon1,pllcon2;
+	//enter slowmode
+	cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
+	cru_writel( CRU_W_MSK(PLL_PWR_DN_SHIFT, 0x01), PLL_CONS(pll_id, 1));
+	
+	sram_udelay(100);
+	
+	pm_pll_wait_lock(pll_id);
+	//return form slow
+	//cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
+	return 0;
+}
+
 #define DDR_SAVE_SP(save_sp)		do { save_sp = ddr_save_sp(((unsigned long)SRAM_DATA_END & (~7))); } while (0)
 #define DDR_RESTORE_SP(save_sp)		do { ddr_save_sp(save_sp); } while (0)
 
@@ -265,6 +281,7 @@ static void __sramfunc rk2928_sram_suspend(void)
 	u32 cru_clksel0_con;
 	u32 clkgt_regs[CRU_CLKGATES_CON_CNT];
 	int i;
+ 	u32 grf_uoc1_con;
 
 	sram_printch('5');
 	ddr_suspend();
@@ -274,7 +291,8 @@ static void __sramfunc rk2928_sram_suspend(void)
 	board_pmu_suspend();
 	sram_printch('7');
 
-
+        grf_uoc1_con = grf_readl(GRF_UOC1_CON4);
+        grf_writel(0x30000000,GRF_UOC1_CON4);
 	for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
 		clkgt_regs[i] = cru_readl(CRU_CLKGATES_CON(i));
 	}
@@ -321,6 +339,7 @@ static void __sramfunc rk2928_sram_suspend(void)
 		cru_writel(clkgt_regs[i] | 0xffff0000, CRU_CLKGATES_CON(i));
 	}
 
+	grf_writel(0x30000000|grf_uoc1_con,GRF_UOC1_CON4);
 	sram_printch('7');
 	board_pmu_resume();
 	rk30_pwm_logic_resume_voltage();
@@ -330,7 +349,6 @@ static void __sramfunc rk2928_sram_suspend(void)
 	ddr_resume();
 	sram_printch('5');
 }
-
 static void noinline rk2928_suspend(void)
 {
 	DDR_SAVE_SP(save_sp);
@@ -441,7 +459,7 @@ static int rk2928_pm_enter(suspend_state_t state)
 	cru_writel(CRU_W_MSK_SETBIT(0x01, PLL_PWR_DN_SHIFT), PLL_CONS(GPLL_ID, 1));//power down gpll
 
 	sram_printch('3');
-	rk30_pwm_suspend_voltage_set();
+//	rk30_pwm_suspend_voltage_set();
 
 	board_gpio_suspend();
 
@@ -452,21 +470,22 @@ static int rk2928_pm_enter(suspend_state_t state)
 	sram_printch('4');
 
 	board_gpio_resume();
-	rk30_pwm_resume_voltage_set();
+//	rk30_pwm_resume_voltage_set();
 	sram_printch('3');
 
 	//gpll
-	cru_writel( CRU_W_MSK(PLL_PWR_DN_SHIFT, 0x01)|gpll_con1, PLL_CONS(GPLL_ID, 1));
+	pm_pll_pwr_up(GPLL_ID);
 	cru_writel(0xffff0000 | clk_sel10, CRU_CLKSELS_CON(10));
 	cru_writel(clk_sel10, CRU_CLKSELS_CON(10));
 	cru_writel((PLL_MODE_MSK(GPLL_ID) << 16) | (PLL_MODE_MSK(GPLL_ID) & cru_mode_con), CRU_MODE_CON);
 
 	//cpll
-	cru_writel( CRU_W_MSK(PLL_PWR_DN_SHIFT, 0x01)|cpll_con1, PLL_CONS(CPLL_ID, 1));
+	if(!(cpll_con1&(0x1<<PLL_PWR_DN_SHIFT)))
+	pm_pll_pwr_up(CPLL_ID);
 	cru_writel((PLL_MODE_MSK(CPLL_ID) << 16) | (PLL_MODE_MSK(CPLL_ID) & cru_mode_con), CRU_MODE_CON);
 
 	//apll
-	cru_writel( CRU_W_MSK(PLL_PWR_DN_SHIFT, 0x01)|apll_con1, PLL_CONS(APLL_ID, 1));
+	pm_pll_pwr_up(APLL_ID);
 	cru_writel(0xffff0000 | clk_sel1, CRU_CLKSELS_CON(1));
 	cru_writel(0xffff0000 | clk_sel0, CRU_CLKSELS_CON(0));
 	cru_writel((PLL_MODE_MSK(APLL_ID) << 16) | (PLL_MODE_MSK(APLL_ID) & cru_mode_con), CRU_MODE_CON);