X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=arch%2Farm%2Fmach-rockchip%2Frockchip.c;h=8473b26a9bd6ef741517add3eeedb813c515cbfb;hb=54b2fd94a4730667d489ec72b77b5fdcfdb16ba1;hp=251c7b9c5f9b6c15ffdab39475d6b7764e9c2fc0;hpb=0e976064256523ca604bd82048ae0e3402ce2467;p=firefly-linux-kernel-4.4.55.git

diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index 251c7b9c5f9b..8473b26a9bd6 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -30,40 +30,27 @@
 #include "pm.h"
 
 #define RK3288_GRF_SOC_CON0 0x244
+#define RK3288_GRF_SOC_CON2 0x24C
 #define RK3288_TIMER6_7_PHYS 0xff810000
 
 static void __init rockchip_timer_init(void)
 {
 	if (of_machine_is_compatible("rockchip,rk3288")) {
 		struct regmap *grf;
-		void __iomem *reg_base;
-
-		/*
-		 * Most/all uboot versions for rk3288 don't enable timer7
-		 * which is needed for the architected timer to work.
-		 * So make sure it is running during early boot.
-		 */
-		reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K);
-		if (reg_base) {
-			writel(0, reg_base + 0x30);
-			writel(0xffffffff, reg_base + 0x20);
-			writel(0xffffffff, reg_base + 0x24);
-			writel(1, reg_base + 0x30);
-			dsb();
-			iounmap(reg_base);
-		} else {
-			pr_err("rockchip: could not map timer7 registers\n");
-		}
 
 		/*
 		 * Disable auto jtag/sdmmc switching that causes issues
 		 * with the mmc controllers making them unreliable
 		 */
 		grf = syscon_regmap_lookup_by_compatible("rockchip,rk3288-grf");
-		if (!IS_ERR(grf))
+		if (!IS_ERR(grf)) {
 			regmap_write(grf, RK3288_GRF_SOC_CON0, 0x10000000);
-		else
+
+			/* Set pwm_sel to RK design PWM; affects all PWMs */
+			regmap_write(grf, RK3288_GRF_SOC_CON2, 0x00010001);
+		} else {
 			pr_err("rockchip: could not get grf syscon\n");
+                }
 	}
 
 	of_clk_init(NULL);