X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=arch%2Farm64%2Fboot%2Fdts%2Frockchip%2Frk3399.dtsi;h=3acdcc3fb4a4f4d39842711c1fc18644380c8714;hb=941e22553dc5b8ddd0d363296499966c7ad29818;hp=679f8fe1a329bebf68995787dde6be8864473d85;hpb=f9ae5d202b3953b5d69e860e540a6f53df7015b5;p=firefly-linux-kernel-4.4.55.git diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 679f8fe1a329..3acdcc3fb4a4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -46,7 +46,8 @@ #include #include #include -#include +#include +#include #include #include "rk3399-dram-default-timing.dtsi" @@ -75,11 +76,6 @@ serial4 = &uart4; }; - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - cpus { #address-cells = <2>; #size-cells = <0>; @@ -118,9 +114,7 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; clocks = <&cru ARMCLKL>; - cpu-idle-states = <&cpu_sleep>; - operating-points-v2 = <&cluster0_opp>; - sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_l1: cpu@1 { @@ -129,9 +123,7 @@ reg = <0x0 0x1>; enable-method = "psci"; clocks = <&cru ARMCLKL>; - cpu-idle-states = <&cpu_sleep>; - operating-points-v2 = <&cluster0_opp>; - sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_l2: cpu@2 { @@ -140,9 +132,7 @@ reg = <0x0 0x2>; enable-method = "psci"; clocks = <&cru ARMCLKL>; - cpu-idle-states = <&cpu_sleep>; - operating-points-v2 = <&cluster0_opp>; - sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_l3: cpu@3 { @@ -151,9 +141,7 @@ reg = <0x0 0x3>; enable-method = "psci"; clocks = <&cru ARMCLKL>; - cpu-idle-states = <&cpu_sleep>; - operating-points-v2 = <&cluster0_opp>; - sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_b0: cpu@100 { @@ -164,9 +152,7 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; clocks = <&cru ARMCLKB>; - cpu-idle-states = <&cpu_sleep>; - operating-points-v2 = <&cluster1_opp>; - sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_b1: cpu@101 { @@ -175,83 +161,76 @@ reg = <0x0 0x101>; enable-method = "psci"; clocks = <&cru ARMCLKB>; - cpu-idle-states = <&cpu_sleep>; - operating-points-v2 = <&cluster1_opp>; - sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; idle-states { entry-method = "psci"; - cpu_sleep: cpu-sleep-0 { + + CPU_SLEEP: cpu-sleep { compatible = "arm,idle-state"; local-timer-stop; arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <350>; - exit-latency-us = <600>; - min-residency-us = <1150>; + entry-latency-us = <120>; + exit-latency-us = <250>; + min-residency-us = <900>; }; - }; - - /include/ "rk3399-sched-energy.dtsi" + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + }; }; - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp@408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <800000>; - clock-latency-ns = <40000>; - }; - opp@600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <800000>; + cpu_avs: cpu-avs { + cluster0-avs { + cluster-id = <0>; + min-volt = <800000>; /* uV */ + min-freq = <408000>; /* KHz */ + leakage-adjust-volt = < + /* mA mA uV */ + 0 254 0 + >; + nvmem-cells = <&cpul_leakage>; + nvmem-cell-names = "cpu_leakage"; }; - opp@816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <800000>; - }; - opp@1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <875000>; - }; - opp@1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <925000>; - }; - opp@1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1025000>; + cluster1-avs { + cluster-id = <1>; + min-volt = <800000>; /* uV */ + min-freq = <408000>; /* KHz */ + leakage-adjust-volt = < + /* mA mA uV */ + 0 254 0 + >; + nvmem-cells = <&cpub_leakage>; + nvmem-cell-names = "cpu_leakage"; }; }; - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + pmu_a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; + }; - opp@408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <800000>; - clock-latency-ns = <40000>; - }; - opp@600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <800000>; - }; - opp@816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <800000>; - }; - opp@1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <850000>; - }; - opp@1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <925000>; - }; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <&efuse_id>; + nvmem-cell-names = "id"; }; timer { @@ -262,21 +241,25 @@ ; }; - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; }; - pmu_a72 { - compatible = "arm,cortex-a72-pmu"; - interrupts = ; + dummy_cpll: dummy_cpll { + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "dummy_cpll"; + #clock-cells = <0>; }; - xin24m: xin24m { + dummy_vpll: dummy_vpll { compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "dummy_vpll"; #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; }; amba { @@ -308,7 +291,7 @@ }; }; - gmac: eth@fe300000 { + gmac: ethernet@fe300000 { compatible = "rockchip,rk3399-gmac"; reg = <0x0 0xfe300000 0x0 0x10000>; rockchip,grf = <&grf>; @@ -485,6 +468,46 @@ }; }; + cdn_dp: dp@fec00000 { + compatible = "rockchip,rk3399-cdn-dp"; + reg = <0x0 0xfec00000 0x0 0x100000>; + interrupts = ; + clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, + <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; + clock-names = "core-clk", "pclk", "spdif", "grf"; + assigned-clocks = <&cru SCLK_DP_CORE>; + assigned-clock-rates = <100000000>; + power-domains = <&power RK3399_PD_HDCP>; + phys = <&tcphy0_dp>, <&tcphy1_dp>; + resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, + <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; + reset-names = "spdif", "dptx", "apb", "core"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dp_in: port { + #address-cells = <1>; + #size-cells = <0>; + dp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_dp>; + }; + + dp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_dp>; + }; + }; + }; + }; + gic: interrupt-controller@fee00000 { compatible = "arm,gic-v3"; #interrupt-cells = <4>; @@ -506,11 +529,11 @@ }; ppi-partitions { - part0: interrupt-partition-0 { + ppi_cluster0: interrupt-partition-0 { affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; }; - part1: interrupt-partition-1 { + ppi_cluster1: interrupt-partition-1 { affinity = <&cpu_b0 &cpu_b1>; }; }; @@ -523,6 +546,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; }; @@ -734,7 +759,7 @@ status = "disabled"; }; - thermal-zones { + thermal_zones: thermal-zones { soc_thermal: soc-thermal { polling-delay-passive = <20>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ @@ -999,7 +1024,8 @@ }; pd_gmac@RK3399_PD_GMAC { reg = ; - clocks = <&cru ACLK_GMAC>; + clocks = <&cru ACLK_GMAC>, + <&cru PCLK_GMAC>; pm_qos = <&qos_gmac>; }; pd_perihp@RK3399_PD_PERIHP { @@ -1056,6 +1082,16 @@ pm_qos = <&qos_isp1_m0>, <&qos_isp1_m1>; }; + pd_tcpc0@RK3399_PD_TCPC0 { + reg = ; + clocks = <&cru SCLK_UPHY0_TCPDCORE>, + <&cru SCLK_UPHY0_TCPDPHY_REF>; + }; + pd_tcpc1@RK3399_PD_TCPC1 { + reg = ; + clocks = <&cru SCLK_UPHY1_TCPDCORE>, + <&cru SCLK_UPHY1_TCPDPHY_REF>; + }; pd_vo@RK3399_PD_VO { reg = ; #address-cells = <1>; @@ -1082,18 +1118,32 @@ pmugrf: syscon@ff320000 { compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff320000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rk3399-pmu-io-voltage-domain"; + status = "disabled"; + }; reboot-mode { compatible = "syscon-reboot-mode"; offset = <0x300>; - mode-bootloader = ; + mode-bootloader = ; mode-charge = ; mode-fastboot = ; - mode-loader = ; + mode-loader = ; mode-normal = ; mode-recovery = ; mode-ums = ; }; + + pmu_pvtm: pmu-pvtm { + compatible = "rockchip,rk3399-pmu-pvtm"; + clocks = <&pmucru SCLK_PVTM_PMU>; + clock-names = "pmu"; + status = "disabled"; + }; }; spi3: spi@ff350000 { @@ -1163,11 +1213,14 @@ compatible = "rockchip,rk3399-pcie"; #address-cells = <3>; #size-cells = <2>; + aspm-no-l0s; clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; clock-names = "aclk", "aclk-perf", "hclk", "pm"; bus-range = <0x0 0x1>; + max-link-speed = <1>; + linux,pci-domain = <0>; msi-map = <0x0 &its 0x0 0x1000>; interrupts = , , @@ -1187,8 +1240,11 @@ <0x0 0xfd000000 0x0 0x1000000>; reg-names = "axi-base", "apb-base"; resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, - <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>; - reset-names = "core", "mgmt", "mgmt-sticky", "pipe"; + <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, + <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, + <&cru SRST_A_PCIE>; + reset-names = "core", "mgmt", "mgmt-sticky", "pipe", + "pm", "pclk", "aclk"; status = "disabled"; pcie0_intc: interrupt-controller { interrupt-controller; @@ -1257,17 +1313,95 @@ clocks = <&cru SCLK_DDRCLK>; clock-names = "dmc_clk"; ddr_timing = <&ddr_timing>; - operating-points-v2 = <&dmc_opp_table>; status = "disabled"; }; - dmc_opp_table: dmc_opp_table { - compatible = "operating-points-v2"; + vpu: vpu_service@ff650000 { + compatible = "rockchip,vpu_service"; + rockchip,grf = <&grf>; + iommus = <&vpu_mmu>; + iommu_enabled = <1>; + reg = <0x0 0xff650000 0x0 0x800>; + interrupts = , + ; + interrupt-names = "irq_dec", "irq_enc"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>; + reset-names = "video_h", "video_a"; + power-domains = <&power RK3399_PD_VCODEC>; + name = "vpu_service"; + dev_mode = <0>; + /* 0 means ion, 1 means drm */ + allocator = <1>; + status = "disabled"; + }; + + vpu_mmu: iommu@ff650800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff650800 0x0 0x40>; + interrupts = ; + interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3399_PD_VCODEC>; + #iommu-cells = <0>; + }; - opp00 { - opp-hz = /bits/ 64 <666000000>; - opp-microvolt = <900000>; - }; + rkvdec: rkvdec@ff660000 { + compatible = "rockchip,rkvdec"; + rockchip,grf = <&grf>; + iommus = <&vdec_mmu>; + iommu_enabled = <1>; + reg = <0x0 0xff660000 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, + <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; + clock-names = "aclk_vcodec", "hclk_vcodec", + "clk_cabac", "clk_core"; + resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>; + reset-names = "video_h", "video_a"; + power-domains = <&power RK3399_PD_VDU>; + dev_mode = <2>; + name = "rkvdec"; + /* 0 means ion, 1 means drm */ + allocator = <1>; + status = "disabled"; + }; + + vdec_mmu: iommu@ff660480 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; + interrupts = ; + interrupt-names = "vdec_mmu"; + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3399_PD_VDU>; + #iommu-cells = <0>; + }; + + iep: iep@ff670000 { + compatible = "rockchip,iep"; + iommu_enabled = <1>; + iommus = <&iep_mmu>; + reg = <0x0 0xff670000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk_iep", "hclk_iep"; + power-domains = <&power RK3399_PD_IEP>; + allocator = <1>; + version = <2>; + status = "disabled"; + }; + + iep_mmu: iommu@ff670800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff670800 0x0 0x40>; + interrupts = ; + interrupt-names = "iep_mmu"; + #iommu-cells = <0>; + status = "disabled"; }; rga: rga@ff680000 { @@ -1292,6 +1426,9 @@ clock-names = "pclk_efuse"; /* Data cells */ + efuse_id: id { + reg = <0x07 0x10>; + }; cpul_leakage: cpul-leakage { reg = <0x1a 0x1>; }; @@ -1331,7 +1468,7 @@ <&cru ACLK_VOP1>, <&cru HCLK_VOP1>, <&cru ARMCLKL>, <&cru ARMCLKB>, <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru PLL_NPLL>, + <&cru ACLK_GPU>, <&cru PLL_NPLL>, <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, <&cru PCLK_PERIHP>, <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, @@ -1342,7 +1479,7 @@ <400000000>, <200000000>, <816000000>, <816000000>, <594000000>, <800000000>, - <1000000000>, + <200000000>, <1000000000>, <150000000>, <75000000>, <37500000>, <100000000>, <100000000>, @@ -1356,6 +1493,11 @@ #address-cells = <1>; #size-cells = <1>; + io_domains: io-domains { + compatible = "rockchip,rk3399-io-voltage-domain"; + status = "disabled"; + }; + emmc_phy: phy@f780 { compatible = "rockchip,rk3399-emmc-phy"; reg = <0xf780 0x24>; @@ -1418,6 +1560,16 @@ status = "disabled"; }; }; + + pvtm: pvtm { + compatible = "rockchip,rk3399-pvtm"; + clocks = <&cru SCLK_PVTM_CORE_L>, + <&cru SCLK_PVTM_CORE_B>, + <&cru SCLK_PVTM_GPU>, + <&cru SCLK_PVTM_DDR>; + clock-names = "core_l", "core_b", "gpu", "ddr"; + status = "disabled"; + }; }; tcphy0: phy@ff7c0000 { @@ -1430,6 +1582,7 @@ clock-names = "tcpdcore", "tcpdphy-ref"; assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; assigned-clock-rates = <50000000>; + power-domains = <&power RK3399_PD_TCPD0>; resets = <&cru SRST_UPHY0>, <&cru SRST_UPHY0_PIPE_L00>, <&cru SRST_P_UPHY0_TCPHY>; @@ -1462,6 +1615,7 @@ clock-names = "tcpdcore", "tcpdphy-ref"; assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; assigned-clock-rates = <50000000>; + power-domains = <&power RK3399_PD_TCPD1>; resets = <&cru SRST_UPHY1>, <&cru SRST_UPHY1_PIPE_L00>, <&cru SRST_P_UPHY1_TCPHY>; @@ -1570,7 +1724,6 @@ clocks = <&cru ACLK_GPU>; clock-names = "clk_mali"; #cooling-cells = <2>; /* min followed by max */ - operating-points-v2 = <&gpu_opp_table>; power-domains = <&power RK3399_PD_GPU>; power-off-delay-ms = <200>; status = "disabled"; @@ -1586,25 +1739,6 @@ }; }; - gpu_opp_table: gpu_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - opp@200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <900000>; - }; - opp@300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <900000>; - }; - opp@400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <900000>; - }; - - }; - vopl: vop@ff8f0000 { compatible = "rockchip,rk3399-vop-lit"; reg = <0x0 0xff8f0000 0x0 0x3efc>; @@ -1635,6 +1769,11 @@ reg = <2>; remote-endpoint = <&hdmi_in_vopl>; }; + + vopl_out_dp: endpoint@3 { + reg = <3>; + remote-endpoint = <&dp_in_vopl>; + }; }; }; @@ -1654,6 +1793,9 @@ reg = <0x0 0xff8f3f00 0x0 0x100>; interrupts = ; interrupt-names = "vopl_mmu"; + clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3399_PD_VOPL>; #iommu-cells = <0>; status = "disabled"; }; @@ -1688,6 +1830,11 @@ reg = <2>; remote-endpoint = <&hdmi_in_vopb>; }; + + vopb_out_dp: endpoint@3 { + reg = <3>; + remote-endpoint = <&dp_in_vopb>; + }; }; }; @@ -1707,20 +1854,49 @@ reg = <0x0 0xff903f00 0x0 0x100>; interrupts = ; interrupt-names = "vopb_mmu"; + clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3399_PD_VOPB>; #iommu-cells = <0>; status = "disabled"; }; + isp0_mmu: iommu@ff914000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; + interrupts = ; + interrupt-names = "isp0_mmu"; + #iommu-cells = <0>; + clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3399_PD_ISP0>; + rk_iommu,disable_reset_quirk; + status = "disabled"; + }; + + isp1_mmu: iommu@ff924000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; + interrupts = ; + interrupt-names = "isp1_mmu"; + #iommu-cells = <0>; + clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3399_PD_ISP1>; + rk_iommu,disable_reset_quirk; + status = "disabled"; + }; + hdmi: hdmi@ff940000 { compatible = "rockchip,rk3399-dw-hdmi"; reg = <0x0 0xff940000 0x0 0x20000>; reg-io-width = <4>; rockchip,grf = <&grf>; - power-domains = <&power RK3399_PD_HDCP>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_i2c_xfer>; + power-domains = <&power RK3399_PD_HDCP>; interrupts = ; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>; + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>; clock-names = "iahb", "isfr", "vpll", "grf"; status = "disabled"; @@ -2514,6 +2690,46 @@ rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none>; }; + + pcie_clkreqn_cpm: pci-clkreqn-cpm { + /* + * Since our pcie doesn't support + * ClockPM(CPM), we want to hack this as + * gpio, so the EP could be able to + * de-assert it along and make ClockPM(CPM) + * work. + */ + rockchip,pins = + <2 26 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_clkreqnb_cpm: pci-clkreqnb-cpm { + rockchip,pins = + <4 24 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; }; + + rockchip_suspend: rockchip-suspend { + compatible = "rockchip,pm-rk3399"; + status = "disabled"; + rockchip,sleep-debug-en = <0>; + rockchip,virtual-poweroff = <0>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + | RKPM_SLP_PERILPPD + | RKPM_SLP_DDR_RET + | RKPM_SLP_PLLPD + | RKPM_SLP_OSC_DIS + | RKPM_SLP_CENTER_PD + | RKPM_SLP_AP_PWROFF + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + ) + >; + }; };