X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=arch%2Farm64%2Fboot%2Fdts%2Frockchip%2Frk3399.dtsi;h=3acdcc3fb4a4f4d39842711c1fc18644380c8714;hb=941e22553dc5b8ddd0d363296499966c7ad29818;hp=7ee53786ce00cc02c130f013290649faa47c567b;hpb=ff7e1390761dba7c224eb2c7da0b01a4a064904b;p=firefly-linux-kernel-4.4.55.git diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 7ee53786ce00..3acdcc3fb4a4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -46,9 +46,12 @@ #include #include #include -#include +#include +#include #include +#include "rk3399-dram-default-timing.dtsi" + / { compatible = "rockchip,rk3399"; @@ -73,11 +76,6 @@ serial4 = &uart4; }; - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - cpus { #address-cells = <2>; #size-cells = <0>; @@ -116,9 +114,7 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; clocks = <&cru ARMCLKL>; - cpu-idle-states = <&cpu_sleep>; - operating-points-v2 = <&cluster0_opp>; - sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_l1: cpu@1 { @@ -127,9 +123,7 @@ reg = <0x0 0x1>; enable-method = "psci"; clocks = <&cru ARMCLKL>; - cpu-idle-states = <&cpu_sleep>; - operating-points-v2 = <&cluster0_opp>; - sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_l2: cpu@2 { @@ -138,9 +132,7 @@ reg = <0x0 0x2>; enable-method = "psci"; clocks = <&cru ARMCLKL>; - cpu-idle-states = <&cpu_sleep>; - operating-points-v2 = <&cluster0_opp>; - sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_l3: cpu@3 { @@ -149,9 +141,7 @@ reg = <0x0 0x3>; enable-method = "psci"; clocks = <&cru ARMCLKL>; - cpu-idle-states = <&cpu_sleep>; - operating-points-v2 = <&cluster0_opp>; - sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_b0: cpu@100 { @@ -162,9 +152,7 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; clocks = <&cru ARMCLKB>; - cpu-idle-states = <&cpu_sleep>; - operating-points-v2 = <&cluster1_opp>; - sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_b1: cpu@101 { @@ -173,83 +161,76 @@ reg = <0x0 0x101>; enable-method = "psci"; clocks = <&cru ARMCLKB>; - cpu-idle-states = <&cpu_sleep>; - operating-points-v2 = <&cluster1_opp>; - sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; idle-states { entry-method = "psci"; - cpu_sleep: cpu-sleep-0 { + + CPU_SLEEP: cpu-sleep { compatible = "arm,idle-state"; local-timer-stop; arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <350>; - exit-latency-us = <600>; - min-residency-us = <1150>; + entry-latency-us = <120>; + exit-latency-us = <250>; + min-residency-us = <900>; }; - }; - - /include/ "rk3399-sched-energy.dtsi" + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + }; }; - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp@408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <800000>; - clock-latency-ns = <40000>; - }; - opp@600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <800000>; - }; - opp@816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <800000>; - }; - opp@1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <875000>; + cpu_avs: cpu-avs { + cluster0-avs { + cluster-id = <0>; + min-volt = <800000>; /* uV */ + min-freq = <408000>; /* KHz */ + leakage-adjust-volt = < + /* mA mA uV */ + 0 254 0 + >; + nvmem-cells = <&cpul_leakage>; + nvmem-cell-names = "cpu_leakage"; }; - opp@1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <925000>; - }; - opp@1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1025000>; + cluster1-avs { + cluster-id = <1>; + min-volt = <800000>; /* uV */ + min-freq = <408000>; /* KHz */ + leakage-adjust-volt = < + /* mA mA uV */ + 0 254 0 + >; + nvmem-cells = <&cpub_leakage>; + nvmem-cell-names = "cpu_leakage"; }; }; - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; - opp@408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <800000>; - clock-latency-ns = <40000>; - }; - opp@600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <800000>; - }; - opp@816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <800000>; - }; - opp@1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <850000>; - }; - opp@1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <925000>; - }; + pmu_a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <&efuse_id>; + nvmem-cell-names = "id"; }; timer { @@ -260,16 +241,25 @@ ; }; - arm-pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - xin24m: xin24m { compatible = "fixed-clock"; - #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + dummy_cpll: dummy_cpll { + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "dummy_cpll"; + #clock-cells = <0>; + }; + + dummy_vpll: dummy_vpll { + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "dummy_vpll"; + #clock-cells = <0>; }; amba { @@ -301,7 +291,7 @@ }; }; - gmac: eth@fe300000 { + gmac: ethernet@fe300000 { compatible = "rockchip,rk3399-gmac"; reg = <0x0 0xfe300000 0x0 0x10000>; rockchip,grf = <&grf>; @@ -317,15 +307,7 @@ "pclk_mac"; resets = <&cru SRST_A_GMAC>; reset-names = "stmmaceth"; - status = "disabled"; - }; - - emmc_phy: phy { - compatible = "rockchip,rk3399-emmc-phy"; - reg-offset = <0xf780>; - #phy-cells = <0>; - rockchip,grf = <&grf>; - ctrl-base = <0xfe330000>; + power-domains = <&power RK3399_PD_GMAC>; status = "disabled"; }; @@ -339,6 +321,7 @@ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; status = "disabled"; }; @@ -352,6 +335,7 @@ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; + power-domains = <&power RK3399_PD_SD>; status = "disabled"; }; @@ -359,13 +343,16 @@ compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; interrupts = ; - clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; - clock-names = "clk_xin", "clk_ahb"; + arasan,soc-ctl-syscon = <&grf>; assigned-clocks = <&cru SCLK_EMMC>; - assigned-clock-parents = <&cru PLL_CPLL>; assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; + clock-names = "clk_xin", "clk_ahb"; + clock-output-names = "emmc_cardclock"; + #clock-cells = <0>; phys = <&emmc_phy>; phy-names = "phy_arasan"; + power-domains = <&power RK3399_PD_EMMC>; status = "disabled"; }; @@ -378,6 +365,7 @@ clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m"; phys = <&u2phy0_host>; phy-names = "usb"; + power-domains = <&power RK3399_PD_PERIHP>; status = "disabled"; }; @@ -390,6 +378,7 @@ clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m"; phys = <&u2phy0_host>; phy-names = "usb"; + power-domains = <&power RK3399_PD_PERIHP>; status = "disabled"; }; @@ -402,6 +391,7 @@ clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m"; phys = <&u2phy1_host>; phy-names = "usb"; + power-domains = <&power RK3399_PD_PERIHP>; status = "disabled"; }; @@ -414,17 +404,19 @@ clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m"; phys = <&u2phy1_host>; phy-names = "usb"; + power-domains = <&power RK3399_PD_PERIHP>; status = "disabled"; }; usbdrd3_0: usb@fe800000 { - compatible = "rockchip,dwc3"; + compatible = "rockchip,rk3399-dwc3"; clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, - <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, - <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; - clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend", - "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf", - "aclk_usb3", "aclk_usb3_grf"; + <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "grf_clk"; + power-domains = <&power RK3399_PD_USB3>; + resets = <&cru SRST_A_USB3_OTG0>; + reset-names = "usb3-otg"; #address-cells = <2>; #size-cells = <2>; ranges; @@ -434,23 +426,27 @@ reg = <0x0 0xfe800000 0x0 0x100000>; interrupts = ; dr_mode = "otg"; + phys = <&u2phy0_otg>, <&tcphy0_usb3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; snps,dis_enblslpm_quirk; - snps,phyif_utmi_16_bits; - snps,dis_u2_freeclk_exists_quirk; - snps,dis_del_phy_power_chg_quirk; - snps,xhci_slow_suspend_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,xhci-slow-suspend-quirk; status = "disabled"; }; }; usbdrd3_1: usb@fe900000 { - compatible = "rockchip,dwc3"; + compatible = "rockchip,rk3399-dwc3"; clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, - <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, - <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; - clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend", - "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf", - "aclk_usb3", "aclk_usb3_grf"; + <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "grf_clk"; + power-domains = <&power RK3399_PD_USB3>; + resets = <&cru SRST_A_USB3_OTG1>; + reset-names = "usb3-otg"; #address-cells = <2>; #size-cells = <2>; ranges; @@ -459,16 +455,59 @@ compatible = "snps,dwc3"; reg = <0x0 0xfe900000 0x0 0x100000>; interrupts = ; - dr_mode = "otg"; + dr_mode = "host"; + phys = <&u2phy1_otg>, <&tcphy1_usb3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; snps,dis_enblslpm_quirk; - snps,phyif_utmi_16_bits; - snps,dis_u2_freeclk_exists_quirk; - snps,dis_del_phy_power_chg_quirk; - snps,xhci_slow_suspend_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,xhci-slow-suspend-quirk; status = "disabled"; }; }; + cdn_dp: dp@fec00000 { + compatible = "rockchip,rk3399-cdn-dp"; + reg = <0x0 0xfec00000 0x0 0x100000>; + interrupts = ; + clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, + <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; + clock-names = "core-clk", "pclk", "spdif", "grf"; + assigned-clocks = <&cru SCLK_DP_CORE>; + assigned-clock-rates = <100000000>; + power-domains = <&power RK3399_PD_HDCP>; + phys = <&tcphy0_dp>, <&tcphy1_dp>; + resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, + <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; + reset-names = "spdif", "dptx", "apb", "core"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dp_in: port { + #address-cells = <1>; + #size-cells = <0>; + dp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_dp>; + }; + + dp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_dp>; + }; + }; + }; + }; + gic: interrupt-controller@fee00000 { compatible = "arm,gic-v3"; #interrupt-cells = <4>; @@ -488,6 +527,16 @@ msi-controller; reg = <0x0 0xfee20000 0x0 0x20000>; }; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu_b0 &cpu_b1>; + }; + }; }; saradc: saradc@ff100000 { @@ -497,6 +546,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; }; @@ -708,7 +759,7 @@ status = "disabled"; }; - thermal-zones { + thermal_zones: thermal-zones { soc_thermal: soc-thermal { polling-delay-passive = <20>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ @@ -784,6 +835,51 @@ status = "disabled"; }; + qos_emmc: qos@ffa58000 { + compatible = "syscon"; + reg = <0x0 0xffa58000 0x0 0x20>; + }; + + qos_gmac: qos@ffa5c000 { + compatible = "syscon"; + reg = <0x0 0xffa5c000 0x0 0x20>; + }; + + qos_pcie: qos@ffa60080 { + compatible = "syscon"; + reg = <0x0 0xffa60080 0x0 0x20>; + }; + + qos_usb_host0: qos@ffa60100 { + compatible = "syscon"; + reg = <0x0 0xffa60100 0x0 0x20>; + }; + + qos_usb_host1: qos@ffa60180 { + compatible = "syscon"; + reg = <0x0 0xffa60180 0x0 0x20>; + }; + + qos_usb_otg0: qos@ffa70000 { + compatible = "syscon"; + reg = <0x0 0xffa70000 0x0 0x20>; + }; + + qos_usb_otg1: qos@ffa70080 { + compatible = "syscon"; + reg = <0x0 0xffa70080 0x0 0x20>; + }; + + qos_sd: qos@ffa74000 { + compatible = "syscon"; + reg = <0x0 0xffa74000 0x0 0x20>; + }; + + qos_sdioaudio: qos@ffa76000 { + compatible = "syscon"; + reg = <0x0 0xffa76000 0x0 0x20>; + }; + qos_hdcp: qos@ffa90000 { compatible = "syscon"; reg = <0x0 0xffa90000 0x0 0x20>; @@ -854,6 +950,11 @@ reg = <0x0 0xffad0000 0x0 0x20>; }; + qos_perihp: qos@ffad8080 { + compatible = "syscon"; + reg = <0x0 0xffad8080 0x0 0x20>; + }; + qos_gpu: qos@ffae0000 { compatible = "syscon"; reg = <0x0 0xffae0000 0x0 0x20>; @@ -912,6 +1013,49 @@ }; /* These power domains are grouped by VD_LOGIC */ + pd_edp@RK3399_PD_EDP { + reg = ; + clocks = <&cru PCLK_EDP_CTRL>; + }; + pd_emmc@RK3399_PD_EMMC { + reg = ; + clocks = <&cru ACLK_EMMC>; + pm_qos = <&qos_emmc>; + }; + pd_gmac@RK3399_PD_GMAC { + reg = ; + clocks = <&cru ACLK_GMAC>, + <&cru PCLK_GMAC>; + pm_qos = <&qos_gmac>; + }; + pd_perihp@RK3399_PD_PERIHP { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru ACLK_PERIHP>; + pm_qos = <&qos_perihp>, + <&qos_pcie>, + <&qos_usb_host0>, + <&qos_usb_host1>; + + pd_sd@RK3399_PD_SD { + reg = ; + clocks = <&cru HCLK_SDMMC>, + <&cru SCLK_SDMMC>; + pm_qos = <&qos_sd>; + }; + }; + pd_sdioaudio@RK3399_PD_SDIOAUDIO { + reg = ; + clocks = <&cru HCLK_SDIO>; + pm_qos = <&qos_sdioaudio>; + }; + pd_usb3@RK3399_PD_USB3 { + reg = ; + clocks = <&cru ACLK_USB3>; + pm_qos = <&qos_usb_otg0>, + <&qos_usb_otg1>; + }; pd_vio@RK3399_PD_VIO { reg = ; #address-cells = <1>; @@ -938,6 +1082,16 @@ pm_qos = <&qos_isp1_m0>, <&qos_isp1_m1>; }; + pd_tcpc0@RK3399_PD_TCPC0 { + reg = ; + clocks = <&cru SCLK_UPHY0_TCPDCORE>, + <&cru SCLK_UPHY0_TCPDPHY_REF>; + }; + pd_tcpc1@RK3399_PD_TCPC1 { + reg = ; + clocks = <&cru SCLK_UPHY1_TCPDCORE>, + <&cru SCLK_UPHY1_TCPDPHY_REF>; + }; pd_vo@RK3399_PD_VO { reg = ; #address-cells = <1>; @@ -964,14 +1118,31 @@ pmugrf: syscon@ff320000 { compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff320000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rk3399-pmu-io-voltage-domain"; + status = "disabled"; + }; reboot-mode { compatible = "syscon-reboot-mode"; offset = <0x300>; + mode-bootloader = ; + mode-charge = ; + mode-fastboot = ; + mode-loader = ; mode-normal = ; mode-recovery = ; - mode-bootloader = ; - mode-loader = ; + mode-ums = ; + }; + + pmu_pvtm: pmu-pvtm { + compatible = "rockchip,rk3399-pmu-pvtm"; + clocks = <&pmucru SCLK_PVTM_PMU>; + clock-names = "pmu"; + status = "disabled"; }; }; @@ -1027,42 +1198,55 @@ status = "disabled"; }; + pcie_phy: phy@e220 { + compatible = "rockchip,rk3399-pcie-phy"; + #phy-cells = <0>; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_PCIEPHY_REF>; + clock-names = "refclk"; + resets = <&cru SRST_PCIEPHY>; + reset-names = "phy"; + status = "disabled"; + }; + pcie0: pcie@f8000000 { compatible = "rockchip,rk3399-pcie"; #address-cells = <3>; #size-cells = <2>; + aspm-no-l0s; clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, - <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>; - clock-names = "aclk_pcie", "aclk_perf_pcie", - "hclk_pcie", "clk_pciephy_ref"; + <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; + clock-names = "aclk", "aclk-perf", + "hclk", "pm"; bus-range = <0x0 0x1>; + max-link-speed = <1>; + linux,pci-domain = <0>; + msi-map = <0x0 &its 0x0 0x1000>; interrupts = , , ; - interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client"; - ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000 - 0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >; - reg = < 0x0 0xf8000000 0x0 0x2000000 >, - < 0x0 0xfd000000 0x0 0x1000000 >; - reg-name = "axi-base", "apb-base"; - resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>, - <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>, - <&cru SRST_PCIE_PIPE>; - reset-names = "phy-rst", "core-rst", "mgmt-rst", - "mgmt-sticky-rst", "pipe-rst"; - rockchip,grf = <&grf>; - pcie-conf = <0xe220>; - pcie-status = <0xe2a4>; - pcie-laneoff = <0xe214>; - msi-parent = <&its>; + interrupt-names = "sys", "legacy", "client"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie0 1>, - <0 0 0 2 &pcie0 2>, - <0 0 0 3 &pcie0 3>, - <0 0 0 4 &pcie0 4>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000 + 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>; + reg = <0x0 0xf8000000 0x0 0x2000000>, + <0x0 0xfd000000 0x0 0x1000000>; + reg-names = "axi-base", "apb-base"; + resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, + <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, + <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, + <&cru SRST_A_PCIE>; + reset-names = "core", "mgmt", "mgmt-sticky", "pipe", + "pm", "pclk", "aclk"; status = "disabled"; - pcie_intc: interrupt-controller { + pcie0_intc: interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; @@ -1113,6 +1297,113 @@ status = "disabled"; }; + dfi: dfi@ff630000 { + reg = <0x00 0xff630000 0x00 0x4000>; + compatible = "rockchip,rk3399-dfi"; + rockchip,pmu = <&pmugrf>; + clocks = <&cru PCLK_DDR_MON>; + clock-names = "pclk_ddr_mon"; + status = "disabled"; + }; + + dmc: dmc { + compatible = "rockchip,rk3399-dmc"; + devfreq-events = <&dfi>; + interrupts = ; + clocks = <&cru SCLK_DDRCLK>; + clock-names = "dmc_clk"; + ddr_timing = <&ddr_timing>; + status = "disabled"; + }; + + vpu: vpu_service@ff650000 { + compatible = "rockchip,vpu_service"; + rockchip,grf = <&grf>; + iommus = <&vpu_mmu>; + iommu_enabled = <1>; + reg = <0x0 0xff650000 0x0 0x800>; + interrupts = , + ; + interrupt-names = "irq_dec", "irq_enc"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>; + reset-names = "video_h", "video_a"; + power-domains = <&power RK3399_PD_VCODEC>; + name = "vpu_service"; + dev_mode = <0>; + /* 0 means ion, 1 means drm */ + allocator = <1>; + status = "disabled"; + }; + + vpu_mmu: iommu@ff650800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff650800 0x0 0x40>; + interrupts = ; + interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3399_PD_VCODEC>; + #iommu-cells = <0>; + }; + + rkvdec: rkvdec@ff660000 { + compatible = "rockchip,rkvdec"; + rockchip,grf = <&grf>; + iommus = <&vdec_mmu>; + iommu_enabled = <1>; + reg = <0x0 0xff660000 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, + <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; + clock-names = "aclk_vcodec", "hclk_vcodec", + "clk_cabac", "clk_core"; + resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>; + reset-names = "video_h", "video_a"; + power-domains = <&power RK3399_PD_VDU>; + dev_mode = <2>; + name = "rkvdec"; + /* 0 means ion, 1 means drm */ + allocator = <1>; + status = "disabled"; + }; + + vdec_mmu: iommu@ff660480 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; + interrupts = ; + interrupt-names = "vdec_mmu"; + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3399_PD_VDU>; + #iommu-cells = <0>; + }; + + iep: iep@ff670000 { + compatible = "rockchip,iep"; + iommu_enabled = <1>; + iommus = <&iep_mmu>; + reg = <0x0 0xff670000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk_iep", "hclk_iep"; + power-domains = <&power RK3399_PD_IEP>; + allocator = <1>; + version = <2>; + status = "disabled"; + }; + + iep_mmu: iommu@ff670800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff670800 0x0 0x40>; + interrupts = ; + interrupt-names = "iep_mmu"; + #iommu-cells = <0>; + status = "disabled"; + }; + rga: rga@ff680000 { compatible = "rockchip,rk3399-rga"; reg = <0x0 0xff680000 0x0 0x10000>; @@ -1122,9 +1413,42 @@ clock-names = "aclk", "hclk", "sclk"; resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3399_PD_RGA>; status = "disabled"; }; + efuse0: efuse@ff690000 { + compatible = "rockchip,rk3399-efuse"; + reg = <0x0 0xff690000 0x0 0x80>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE1024NS>; + clock-names = "pclk_efuse"; + + /* Data cells */ + efuse_id: id { + reg = <0x07 0x10>; + }; + cpul_leakage: cpul-leakage { + reg = <0x1a 0x1>; + }; + cpub_leakage: cpub-leakage { + reg = <0x17 0x1>; + }; + gpu_leakage: gpu-leakage { + reg = <0x18 0x1>; + }; + center_leakage: center-leakage { + reg = <0x19 0x1>; + }; + logic_leakage: logic-leakage { + reg = <0x1b 0x1>; + }; + wafer_info: wafer-info { + reg = <0x1c 0x1>; + }; + }; + pmucru: pmu-clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>; @@ -1144,7 +1468,7 @@ <&cru ACLK_VOP1>, <&cru HCLK_VOP1>, <&cru ARMCLKL>, <&cru ARMCLKB>, <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru PLL_NPLL>, + <&cru ACLK_GPU>, <&cru PLL_NPLL>, <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, <&cru PCLK_PERIHP>, <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, @@ -1155,7 +1479,7 @@ <400000000>, <200000000>, <816000000>, <816000000>, <594000000>, <800000000>, - <1000000000>, + <200000000>, <1000000000>, <150000000>, <75000000>, <37500000>, <100000000>, <100000000>, @@ -1169,6 +1493,20 @@ #address-cells = <1>; #size-cells = <1>; + io_domains: io-domains { + compatible = "rockchip,rk3399-io-voltage-domain"; + status = "disabled"; + }; + + emmc_phy: phy@f780 { + compatible = "rockchip,rk3399-emmc-phy"; + reg = <0xf780 0x24>; + clocks = <&sdhci>; + clock-names = "emmcclk"; + #phy-cells = <0>; + status = "disabled"; + }; + u2phy0: usb2-phy@e450 { compatible = "rockchip,rk3399-usb2phy"; reg = <0xe450 0x10>; @@ -1205,6 +1543,16 @@ clock-output-names = "clk_usbphy1_480m"; status = "disabled"; + u2phy1_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + u2phy1_host: host-port { #phy-cells = <0>; interrupts = ; @@ -1212,51 +1560,87 @@ status = "disabled"; }; }; + + pvtm: pvtm { + compatible = "rockchip,rk3399-pvtm"; + clocks = <&cru SCLK_PVTM_CORE_L>, + <&cru SCLK_PVTM_CORE_B>, + <&cru SCLK_PVTM_GPU>, + <&cru SCLK_PVTM_DDR>; + clock-names = "core_l", "core_b", "gpu", "ddr"; + status = "disabled"; + }; }; tcphy0: phy@ff7c0000 { compatible = "rockchip,rk3399-typec-phy"; reg = <0x0 0xff7c0000 0x0 0x40000>; rockchip,grf = <&grf>; - #phy-cells = <0>; + #phy-cells = <1>; clocks = <&cru SCLK_UPHY0_TCPDCORE>, <&cru SCLK_UPHY0_TCPDPHY_REF>; clock-names = "tcpdcore", "tcpdphy-ref"; + assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; + assigned-clock-rates = <50000000>; + power-domains = <&power RK3399_PD_TCPD0>; resets = <&cru SRST_UPHY0>, <&cru SRST_UPHY0_PIPE_L00>, <&cru SRST_P_UPHY0_TCPHY>; reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; rockchip,typec-conn-dir = <0xe580 0 16>; rockchip,usb3tousb2-en = <0xe580 3 19>; + rockchip,usb3-host-disable = <0x2434 0 16>; + rockchip,usb3-host-port = <0x2434 12 28>; rockchip,external-psm = <0xe588 14 30>; rockchip,pipe-status = <0xe5c0 0 0>; rockchip,uphy-dp-sel = <0x6268 19 19>; status = "disabled"; + + tcphy0_dp: dp-port { + #phy-cells = <0>; + }; + + tcphy0_usb3: usb3-port { + #phy-cells = <0>; + }; }; tcphy1: phy@ff800000 { compatible = "rockchip,rk3399-typec-phy"; reg = <0x0 0xff800000 0x0 0x40000>; rockchip,grf = <&grf>; - #phy-cells = <0>; + #phy-cells = <1>; clocks = <&cru SCLK_UPHY1_TCPDCORE>, <&cru SCLK_UPHY1_TCPDPHY_REF>; clock-names = "tcpdcore", "tcpdphy-ref"; + assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; + assigned-clock-rates = <50000000>; + power-domains = <&power RK3399_PD_TCPD1>; resets = <&cru SRST_UPHY1>, <&cru SRST_UPHY1_PIPE_L00>, <&cru SRST_P_UPHY1_TCPHY>; reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; rockchip,typec-conn-dir = <0xe58c 0 16>; rockchip,usb3tousb2-en = <0xe58c 3 19>; + rockchip,usb3-host-disable = <0x2444 0 16>; + rockchip,usb3-host-port = <0x2444 12 28>; rockchip,external-psm = <0xe594 14 30>; rockchip,pipe-status = <0xe5c0 16 16>; rockchip,uphy-dp-sel = <0x6268 3 19>; status = "disabled"; + + tcphy1_dp: dp-port { + #phy-cells = <0>; + }; + + tcphy1_usb3: usb3-port { + #phy-cells = <0>; + }; }; - watchdog@ff840000 { + watchdog@ff848000 { compatible = "snps,dw-wdt"; - reg = <0x0 0xff840000 0x0 0x100>; + reg = <0x0 0xff848000 0x0 0x100>; clocks = <&cru PCLK_WDT>; interrupts = ; }; @@ -1279,6 +1663,7 @@ clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; pinctrl-names = "default"; pinctrl-0 = <&spdif_bus>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; status = "disabled"; }; @@ -1293,6 +1678,7 @@ clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_8ch_bus>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; status = "disabled"; }; @@ -1306,6 +1692,7 @@ clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; pinctrl-names = "default"; pinctrl-0 = <&i2s1_2ch_bus>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; status = "disabled"; }; @@ -1317,6 +1704,7 @@ dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; status = "disabled"; }; @@ -1336,7 +1724,6 @@ clocks = <&cru ACLK_GPU>; clock-names = "clk_mali"; #cooling-cells = <2>; /* min followed by max */ - operating-points-v2 = <&gpu_opp_table>; power-domains = <&power RK3399_PD_GPU>; power-off-delay-ms = <200>; status = "disabled"; @@ -1352,25 +1739,6 @@ }; }; - gpu_opp_table: gpu_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - opp@200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <900000>; - }; - opp@300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <900000>; - }; - opp@400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <900000>; - }; - - }; - vopl: vop@ff8f0000 { compatible = "rockchip,rk3399-vop-lit"; reg = <0x0 0xff8f0000 0x0 0x3efc>; @@ -1401,14 +1769,33 @@ reg = <2>; remote-endpoint = <&hdmi_in_vopl>; }; + + vopl_out_dp: endpoint@3 { + reg = <3>; + remote-endpoint = <&dp_in_vopl>; + }; }; }; + vop1_pwm: voppwm@ff8f01a0 { + compatible = "rockchip,vop-pwm"; + reg = <0x0 0xff8f01a0 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&vop1_pwm_pin>; + clocks = <&cru SCLK_VOP1_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + vopl_mmu: iommu@ff8f3f00 { compatible = "rockchip,iommu"; reg = <0x0 0xff8f3f00 0x0 0x100>; interrupts = ; interrupt-names = "vopl_mmu"; + clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3399_PD_VOPL>; #iommu-cells = <0>; status = "disabled"; }; @@ -1443,26 +1830,73 @@ reg = <2>; remote-endpoint = <&hdmi_in_vopb>; }; + + vopb_out_dp: endpoint@3 { + reg = <3>; + remote-endpoint = <&dp_in_vopb>; + }; }; }; + vop0_pwm: voppwm@ff9001a0 { + compatible = "rockchip,vop-pwm"; + reg = <0x0 0xff9001a0 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&vop0_pwm_pin>; + clocks = <&cru SCLK_VOP0_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + vopb_mmu: iommu@ff903f00 { compatible = "rockchip,iommu"; reg = <0x0 0xff903f00 0x0 0x100>; interrupts = ; interrupt-names = "vopb_mmu"; + clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3399_PD_VOPB>; #iommu-cells = <0>; status = "disabled"; }; + isp0_mmu: iommu@ff914000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; + interrupts = ; + interrupt-names = "isp0_mmu"; + #iommu-cells = <0>; + clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3399_PD_ISP0>; + rk_iommu,disable_reset_quirk; + status = "disabled"; + }; + + isp1_mmu: iommu@ff924000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; + interrupts = ; + interrupt-names = "isp1_mmu"; + #iommu-cells = <0>; + clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3399_PD_ISP1>; + rk_iommu,disable_reset_quirk; + status = "disabled"; + }; + hdmi: hdmi@ff940000 { compatible = "rockchip,rk3399-dw-hdmi"; reg = <0x0 0xff940000 0x0 0x20000>; reg-io-width = <4>; rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_i2c_xfer>; power-domains = <&power RK3399_PD_HDCP>; interrupts = ; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>; + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>; clock-names = "iahb", "isfr", "vpll", "grf"; status = "disabled"; @@ -1522,6 +1956,7 @@ interrupts = ; clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>; clock-names = "dp", "pclk"; + power-domains = <&power RK3399_PD_EDP>; resets = <&cru SRST_P_EDP_CTRL>; reset-names = "dp"; rockchip,grf = <&grf>; @@ -1642,6 +2077,21 @@ bias-disable; }; + pcfg_pull_up_20ma: pcfg-pull-up-20ma { + bias-pull-up; + drive-strength = <20>; + }; + + pcfg_pull_none_20ma: pcfg-pull-none-20ma { + bias-disable; + drive-strength = <20>; + }; + + pcfg_pull_none_18ma: pcfg-pull-none-18ma { + bias-disable; + drive-strength = <18>; + }; + pcfg_pull_none_12ma: pcfg-pull-none-12ma { bias-disable; drive-strength = <12>; @@ -1672,6 +2122,18 @@ drive-strength = <13>; }; + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_input: pcfg-input { + input-enable; + }; + emmc { emmc_pwr: emmc-pwr { rockchip,pins = @@ -2228,6 +2690,46 @@ rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none>; }; + + pcie_clkreqn_cpm: pci-clkreqn-cpm { + /* + * Since our pcie doesn't support + * ClockPM(CPM), we want to hack this as + * gpio, so the EP could be able to + * de-assert it along and make ClockPM(CPM) + * work. + */ + rockchip,pins = + <2 26 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_clkreqnb_cpm: pci-clkreqnb-cpm { + rockchip,pins = + <4 24 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; }; + + rockchip_suspend: rockchip-suspend { + compatible = "rockchip,pm-rk3399"; + status = "disabled"; + rockchip,sleep-debug-en = <0>; + rockchip,virtual-poweroff = <0>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + | RKPM_SLP_PERILPPD + | RKPM_SLP_DDR_RET + | RKPM_SLP_PLLPD + | RKPM_SLP_OSC_DIS + | RKPM_SLP_CENTER_PD + | RKPM_SLP_AP_PWROFF + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + ) + >; + }; };