X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=docs%2FAtomics.html;h=fc15e27c39cd765233d8e7d40447e86a8b0eab33;hb=2929de422e4f0ca80e4f428ab970f06616e1d9b2;hp=3adeafc7100b27b9e8137481dbd828c41f22f994;hpb=e2d8cf77c8df45768a3902a97cd357dcf2a5d719;p=oota-llvm.git diff --git a/docs/Atomics.html b/docs/Atomics.html index 3adeafc7100..fc15e27c39c 100644 --- a/docs/Atomics.html +++ b/docs/Atomics.html @@ -14,9 +14,9 @@
The atomic instructions are designed specifically to provide readable IR and optimized code generation for the following:
<atomic>
header.<atomic>
header.
+ (C++0x draft available here.)
+ (C1x draft available here)volatile
and
- regular shared variables.__sync_*
builtins.__sync_*
builtins.
+ (Description)static
variables with non-trivial constructors in C++.Atomic and volatile in the IR are orthogonal; "volatile" is the C/C++ + volatile, which ensures that every volatile load and store happens and is + performed in the stated order. A couple examples: if a + SequentiallyConsistent store is immediately followed by another + SequentiallyConsistent store to the same address, the first store can + be erased. This transformation is not allowed for a pair of volatile + stores. On the other hand, a non-volatile non-atomic load can be moved + across a volatile load freely, but not an Acquire load.
+This document is intended to provide a guide to anyone either writing a frontend for LLVM or working on optimization passes for LLVM with a guide for how to deal with instructions with special semantics in the presence of @@ -62,31 +75,95 @@ instructions has been clarified in the IR.
The basic 'load'
and 'store'
allow a variety of
- optimizations, but can have unintuitive results in a concurrent environment.
- For a frontend writer, the rule is essentially that all memory accessed
- with basic loads and stores by multiple threads should be protected by a
- lock or other synchronization; otherwise, you are likely to run into
- undefined behavior. (Do not use volatile as a substitute for atomics; it
- might work on some platforms, but does not provide the necessary guarantees
- in general.)
From the optimizer's point of view, the rule is that if there
- are not any instructions with atomic ordering involved, concurrency does not
- matter, with one exception: if a variable might be visible to another
+ are not any instructions with atomic ordering involved, concurrency does
+ not matter, with one exception: if a variable might be visible to another
thread or signal handler, a store cannot be inserted along a path where it
- might not execute otherwise. Note that speculative loads are allowed;
- a load which is part of a race returns undef
, but is not
- undefined behavior.
+/* C code, for readability; run through clang -O2 -S -emit-llvm to get + equivalent IR */ +int x; +void f(int* a) { + for (int i = 0; i < 100; i++) { + if (a[i]) + x += 1; + } +} ++ +
The following is equivalent in non-concurrent situations:
+ ++int x; +void f(int* a) { + int xtemp = x; + for (int i = 0; i < 100; i++) { + if (a[i]) + xtemp += 1; + } + x = xtemp; +} ++ +
However, LLVM is not allowed to transform the former to the latter: it could + indirectly introduce undefined behavior if another thread can access x at + the same time. (This example is particularly of interest because before the + concurrency model was implemented, LLVM would perform this + transformation.)
+ +Note that speculative loads are allowed; a load which
+ is part of a race returns undef
, but does not have undefined
+ behavior.
For cases where simple loads and stores are not sufficient, LLVM provides - atomic loads and stores with varying levels of guarantees.
+ various atomic instructions. The exact guarantees provided depend on the + ordering; see Atomic orderings + +load atomic
and store atomic
provide the same
+ basic functionality as non-atomic loads and stores, but provide additional
+ guarantees in situations where threads and signals are involved.
cmpxchg
and atomicrmw
are essentially like an
+ atomic load followed by an atomic store (where the store is conditional for
+ cmpxchg
), but no other memory operation can happen on any thread
+ between the load and store. Note that LLVM's cmpxchg does not provide quite
+ as many options as the C++0x version.
A fence
provides Acquire and/or Release ordering which is not
+ part of another operation; it is normally used along with Monotonic memory
+ operations. A Monotonic load followed by an Acquire fence is roughly
+ equivalent to an Acquire load.
Frontends generating atomic instructions generally need to be aware of the + target to some degree; atomic instructions are guaranteed to be lock-free, + and therefore an instruction which is wider than the target natively supports + can be impossible to generate.
In order to achieve a balance between performance and necessary guarantees, there are six levels of atomicity. They are listed in order of strength; each level includes all the guarantees of the previous level except for - Acquire/Release.
+ Acquire/Release. (See also LangRef.) + + +NotAtomic is the obvious, a load or store which is not atomic. (This isn't + really a level of atomicity, but is listed here for comparison.) This is + essentially a regular load or store. If there is a race on a given memory + location, loads from that location return undef.
+ +Unordered is the lowest level of atomicity. It essentially guarantees that - races produce somewhat sane results instead of having undefined behavior. - This is intended to match the Java memory model for shared variables. It - cannot be used for synchronization, but is useful for Java and other - "safe" languages which need to guarantee that the generated code never - exhibits undefined behavior. Note that this guarantee is cheap on common - platforms for loads of a native width, but can be expensive or unavailable - for wider loads, like a 64-bit load on ARM. (A frontend for a "safe" - language would normally split a 64-bit load on ARM into two 32-bit - unordered loads.) In terms of the optimizer, this prohibits any - transformation that transforms a single load into multiple loads, - transforms a store into multiple stores, narrows a store, or stores a - value which would not be stored otherwise. Some examples of unsafe - optimizations are narrowing an assignment into a bitfield, rematerializing - a load, and turning loads and stores into a memcpy call. Reordering - unordered operations is safe, though, and optimizers should take - advantage of that because unordered operations are common in - languages that need them.
+ races produce somewhat sane results instead of having undefined behavior. + It also guarantees the operation to be lock-free, so it do not depend on + the data being part of a special atomic structure or depend on a separate + per-process global lock. Note that code generation will fail for + unsupported atomic operations; if you need such an operation, use explicit + locking. + +LDRD
on ARM).Monotonic is the weakest level of atomicity that can be used in
synchronization primitives, although it does not provide any general
synchronization. It essentially guarantees that if you take all the
operations affecting a specific address, a consistent ordering exists.
- This corresponds to the C++0x/C1x memory_order_relaxed
; see
- those standards for the exact definition. If you are writing a frontend, do
- not use the low-level synchronization primitives unless you are compiling
- a language which requires it or are sure a given pattern is correct. In
- terms of the optimizer, this can be treated as a read+write on the relevant
- memory location (and alias analysis will take advantage of that). In
- addition, it is legal to reorder non-atomic and Unordered loads around
- Monotonic loads. CSE/DSE and a few other optimizations are allowed, but
- Monotonic operations are unlikely to be used in ways which would make
- those optimizations useful.
memory_order_relaxed
;
+ see those standards for the exact definition.
+ fence
.cmpxchg
and
+ atomicrmw
are required to appear as a single operation.Acquire provides a barrier of the sort necessary to acquire a lock to access
- other memory with normal loads and stores. This corresponds to the
- C++0x/C1x memory_order_acquire
. It should also be used for
- C++0x/C1x memory_order_consume
. This is a low-level
- synchronization primitive. In general, optimizers should treat this like
- a nothrow call.
memory_order_acquire
. It
+ should also be used for C++0x/C1x memory_order_consume
.
+ dmb
on ARM,
+ sync
on PowerPC, etc.). Putting such a fence after the
+ equivalent Monotonic operation is sufficient to maintain Acquire
+ semantics for a memory operation.Release is similar to Acquire, but with a barrier of the sort necessary to
- release a lock. This corresponds to the C++0x/C1x
- memory_order_release
. In general, optimizers should treat this
- like a nothrow call.
AcquireRelease (acq_rel
in IR) provides both an Acquire and a Release barrier.
- This corresponds to the C++0x/C1x memory_order_acq_rel
. In general,
- optimizers should treat this like a nothrow call.
SequentiallyConsistent (seq_cst
in IR) provides Acquire and/or
- Release semantics, and in addition guarantees a total ordering exists with
- all other SequentiallyConsistent operations. This corresponds to the
- C++0x/C1x memory_order_seq_cst
, and Java volatile. The intent
- of this ordering level is to provide a programming model which is relatively
- easy to understand. In general, optimizers should treat this like a
- nothrow call.
memory_order_release
.cmpxchg
and atomicrmw
are essentially like an
- atomic load followed by an atomic store (where the store is conditional for
- cmpxchg
), but no other memory operation can happen between
- the load and store. Note that our cmpxchg does not have quite as many
- options for making cmpxchg weaker as the C++0x version.
AcquireRelease (acq_rel
in IR) provides both an Acquire and a
+ Release barrier (for fences and operations which both read and write memory).
+
+
memory_order_acq_rel
.
+ A fence
provides Acquire and/or Release ordering which is not
- part of another operation; it is normally used along with Monotonic memory
- operations. A Monotonic load followed by an Acquire fence is roughly
- equivalent to an Acquire load.
Frontends generating atomic instructions generally need to be aware of the - target to some degree; atomic instructions are guaranteed to be lock-free, - and therefore an instruction which is wider than the target natively supports - can be impossible to generate.
+ +SequentiallyConsistent (seq_cst
in IR) provides
+ Acquire semantics for loads and Release semantics for
+ stores. Additionally, it guarantees that a total ordering exists
+ between all SequentiallyConsistent operations.
+
+
memory_order_seq_cst
,
+ Java volatile, and the gcc-compatible __sync_*
builtins
+ which do not specify otherwise.
+ There are essentially two components to supporting atomic operations. The - first is making sure to query isSimple() or isUnordered() instead - of isVolatile() before transforming an operation. The other piece is - making sure that a transform does not end up replacing, for example, an - Unordered operation with a non-atomic operation. Most of the other - necessary checks automatically fall out from existing predicates and - alias analysis queries.
+To support optimizing around atomic operations, make sure you are using + the right predicates; everything should work if that is done. If your + pass should optimize some atomic operations (Unordered operations in + particular), make sure it doesn't replace an atomic load or store with + a non-atomic operation.
Some examples of how optimizations interact with various kinds of atomic operations: @@ -257,6 +515,15 @@ instructions has been clarified in the IR.
handles anything marked volatile very conservatively. This should get fixed at some point. +Common architectures have some way of representing at least a pointer-sized
+ lock-free cmpxchg
; such an operation can be used to implement
+ all the other atomic operations which can be represented in IR up to that
+ size. Backends are expected to implement all those operations, but not
+ operations which cannot be implemented in a lock-free manner. It is
+ expected that backends will give an error when given an operation which
+ cannot be implemented. (The LLVM code generator is not very helpful here
+ at the moment, but hopefully that will change.)
The implementation of atomics on LL/SC architectures (like ARM) is currently a bit of a mess; there is a lot of copy-pasted code across targets, and the representation is relatively unsuited to optimization (it would be nice @@ -278,8 +545,11 @@ instructions has been clarified in the IR.
On ARM, MIPS, and many other RISC architectures, Acquire, Release, and
SequentiallyConsistent semantics require barrier instructions
for every such operation. Loads and stores generate normal instructions.
- atomicrmw
and cmpxchg
generate LL/SC loops.
cmpxchg
and atomicrmw
can be represented using
+ a loop with LL/SC-style instructions which take some sort of exclusive
+ lock on a cache line (LDREX
and STREX
on
+ ARM, etc.). At the moment, the IR does not provide any way to represent a
+ weak cmpxchg
which would not require a loop.