The MRegisterInfo class (which will eventually be renamed to -TargetRegisterInfo) is used to describe the register file of the -target and any interactions between the registers.
+The TargetRegisterInfo class is used to describe the register +file of the target and any interactions between the registers.
Registers in the code generator are represented in the code generator by unsigned integers. Physical registers (those that actually exist in the target @@ -408,8 +408,8 @@ register (used for assembly output and debugging dumps) and a set of aliases (used to indicate whether one register overlaps with another).
-In addition to the per-register description, the MRegisterInfo class -exposes a set of processor specific register classes (instances of the +
In addition to the per-register description, the TargetRegisterInfo +class exposes a set of processor specific register classes (instances of the TargetRegisterClass class). Each register class contains sets of registers that have the same properties (for example, they are all 32-bit integer registers). Each SSA virtual register created by the instruction @@ -621,9 +621,9 @@ copies a virtual register into or out of a physical register when needed.
-int %test(int %X, int %Y) {
- %Z = div int %X, %Y
- ret int %Z
+define i32 @test(i32 %X, i32 %Y) {
+ %Z = udiv i32 %X, %Y
+ ret i32 %Z
}
Instruction Selection is the process of translating LLVM code presented to the code generator into target-specific machine instructions. There are several -well-known ways to do this in the literature. In LLVM there are two main forms: -the SelectionDAG based instruction selector framework and an old-style 'simple' -instruction selector, which effectively peephole selects each LLVM instruction -into a series of machine instructions. We recommend that all targets use the -SelectionDAG infrastructure. +well-known ways to do this in the literature. LLVM uses a SelectionDAG based +instruction selector.
Portions of the DAG instruction selector are generated from the target description (*.td) files. Our goal is for the entire instruction -selector to be generated from these .td files.
+selector to be generated from these .td files, though currently +there are still things that require custom C++ code. @@ -793,7 +790,8 @@ to the node defining the used value. Because nodes may define multiple values, edges are represented by instances of the SDOperand class, which is a <SDNode, unsigned> pair, indicating the node and result value being used, respectively. Each value produced by an SDNode has -an associated MVT::ValueType indicating what type the value is. +an associated MVT (Machine Value Type) indicating what the type of the +value is.SelectionDAGs contain two different kinds of values: those that represent data flow and those that represent control flow dependencies. Data values are @@ -865,7 +863,11 @@ of the code compiled (if you only get errors printed to the console while using this, you probably need to configure your system to add support for it). The -view-sched-dags option views the SelectionDAG output from the Select phase and input to the Scheduler -phase.
+phase. The -view-sunit-dags option views the ScheduleDAG, which is +based on the final SelectionDAG, with nodes that must be scheduled as a unit +bundled together into a single node, and with immediate operands and other +nodes that aren't relevent for scheduling omitted. + @@ -1111,7 +1113,8 @@ primarily because it is a work in progress and is not yet finished:Physical registers, in LLVM, are grouped in Register Classes. @@ -1308,10 +1311,10 @@ this code can be used: bool RegMapping_Fer::compatible_class(MachineFunction &mf, unsigned v_reg, unsigned p_reg) { - assert(MRegisterInfo::isPhysicalRegister(p_reg) && + assert(TargetRegisterInfo::isPhysicalRegister(p_reg) && "Target register must be physical"); - const TargetRegisterClass *trc = mf.getSSARegMap()->getRegClass(v_reg); - return trc->contains(p_reg); + const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg); + return trc->contains(p_reg); } @@ -1333,14 +1336,14 @@ physical registers, different virtual registers never share the same number. The smallest virtual register is normally assigned the number 1024. This may change, so, in order to know which is the first virtual register, you should access -MRegisterInfo::FirstVirtualRegister. Any register whose +TargetRegisterInfo::FirstVirtualRegister. Any register whose number is greater than or equal to -MRegisterInfo::FirstVirtualRegister is considered a virtual +TargetRegisterInfo::FirstVirtualRegister is considered a virtual register. Whereas physical registers are statically defined in a TargetRegisterInfo.td file and cannot be created by the application developer, that is not the case with virtual registers. In order to create new virtual registers, use the method -SSARegMap::createVirtualRegister(). This method will return a +MachineRegisterInfo::createVirtualRegister(). This method will return a virtual register with the highest code.
@@ -1392,7 +1395,7 @@ overwritten by the values of virtual registers while still alive.There are two ways to map virtual registers to physical registers (or to memory slots). The first way, that we will call direct mapping, -is based on the use of methods of the classes MRegisterInfo, +is based on the use of methods of the classes TargetRegisterInfo, and MachineOperand. The second way, that we will call indirect mapping, relies on the VirtRegMap class in order to insert loads and stores sending and getting values to and from @@ -1406,8 +1409,8 @@ target function being compiled in order to get and store values in memory. To assign a physical register to a virtual register present in a given operand, use MachineOperand::setReg(p_reg). To insert a store instruction, use -MRegisterInfo::storeRegToStackSlot(...), and to insert a load -instruction, use MRegisterInfo::loadRegFromStackSlot.
+TargetRegisterInfo::storeRegToStackSlot(...), and to insert a load +instruction, use TargetRegisterInfo::loadRegFromStackSlot.The indirect mapping shields the application developer from the
complexities of inserting load and store instructions. In order to map
@@ -1465,12 +1468,12 @@ instance, in situations where an instruction such as %a = ADD %b
%a = MOVE %b
-%a = ADD %a %b
+%a = ADD %a %c
Notice that, internally, the second instruction is represented as -ADD %a[def/use] %b. I.e., the register operand %a is +ADD %a[def/use] %c. I.e., the register operand %a is both used and defined by the instruction.
@@ -1527,7 +1530,7 @@ instance, a sequence of instructions such as:Instructions can be folded with the -MRegisterInfo::foldMemoryOperand(...) method. Care must be +TargetRegisterInfo::foldMemoryOperand(...) method. Care must be taken when folding instructions; a folded instruction can be quite different from the original instruction. See LiveIntervals::addIntervalsForSpills in @@ -1619,7 +1622,51 @@ are specific to the code generator for a particular target.
+ + + +Tail call optimization, callee reusing the stack of the caller, is currently supported on x86/x86-64 and PowerPC. It is performed if: +
x86/x86-64 constraints: +
PowerPC constraints: +
Example:
+Call as llc -tailcallopt test.ll. +
+declare fastcc i32 @tailcallee(i32 inreg %a1, i32 inreg %a2, i32 %a3, i32 %a4)
+
+define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
+ %l1 = add i32 %in1, %in2
+ %tmp = tail call fastcc i32 @tailcallee(i32 %in1 inreg, i32 %in2 inreg, i32 %in1, i32 %l1)
+ ret i32 %tmp
+}
+ Implications of -tailcallopt:
+To support tail call optimization in situations where the callee has more arguments than the caller a 'callee pops arguments' convention is used. This currently causes each fastcc call that is not tail call optimized (because one or more of above constraints are not met) to be followed by a readjustment of the stack. So performance might be worse in such cases.
+On x86 and x86-64 one register is reserved for indirect tail calls (e.g via a function pointer). So there is one less register for integer argument passing. For x86 this means 2 registers (if inreg parameter attribute is used) and for x86-64 this means 5 register are used.
+The X86 code generator lives in the lib/Target/X86 directory. This -code generator currently targets a generic P6-like processor. As such, it -produces a few P6-and-above instructions (like conditional moves), but it does -not make use of newer features like MMX or SSE. In the future, the X86 backend -will have sub-target support added for specific processor families and -implementations.
+code generator is capable of targeting a variety of x86-32 and x86-64 +processors, and includes support for ISA extensions such as MMX and SSE. +