Important Note: For historical reasons, the LLVM SparcV9 code generator uses almost entirely different code paths than described in this document. For this reason, there are some deprecated interfaces (such as -TargetRegInfo and TargetSchedInfo), which are only used by the +TargetSchedInfo), which are only used by the V9 backend and should not be used by any other targets. Also, all code in the lib/Target/SparcV9 directory and subdirectories should be considered deprecated, and should not be used as the basis for future code generator work. @@ -159,41 +188,54 @@ predictable completion date.
The LLVM target-indendent code generator is designed to support efficient and +
The LLVM target-independent code generator is designed to support efficient and quality code generation for standard register-based microprocessors. Code generation in this model is divided into the following stages:
@@ -227,13 +269,25 @@ targets with unusual requirements can be supported with custom passes as needed.
The target description classes require a detailed description of the target architecture. These target descriptions often have a large amount of common -information (e.g., an add instruction is almost identical to a sub instruction). +information (e.g., an add instruction is almost identical to a +sub instruction). In order to allow the maximum amount of commonality to be factored out, the LLVM code generator uses the TableGen tool to -describe big chunks of the target machine, which allows the use of domain- and -target-specific abstractions to reduce the amount of repetition. +describe big chunks of the target machine, which allows the use of +domain-specific and target-specific abstractions to reduce the amount of +repetition.
+As LLVM continues to be developed and refined, we plan to move more and more +of the target description to be in .td form. Doing so gives us a +number of advantages. The most important is that it makes it easier to port +LLVM, because it reduces the amount of C++ code that has to be written and the +surface area of the code generator that needs to be understood before someone +can get in an get something working. Second, it is also important to us because +it makes it easier to change things: in particular, if tables and other things +are all emitted by tblgen, we only need to change one place (tblgen) to update +all of the targets to a new interface.
+The LLVM target description classes (which are located in the include/llvm/Target directory) provide an abstract description of the -target machine, independent of any particular client. These classes are -designed to capture the abstract properties of the target (such as what -instruction and registers it has), and do not incorporate any particular pieces -of code generation algorithms (these interfaces do not take interference graphs -as inputs or other algorithm-specific data structures).
+target machine; independent of any particular client. These classes are +designed to capture the abstract properties of the target (such as the +instructions and registers it has), and do not incorporate any particular pieces +of code generation algorithms.All of the target description classes (except the TargetData class) are designed to be subclassed by @@ -270,8 +323,9 @@ should be implemented by the target.
The TargetMachine class provides virtual methods that are used to access the target-specific implementations of the various target description -classes (with the getInstrInfo, getRegisterInfo, -getFrameInfo, ... methods). This class is designed to be specialized by +classes via the get*Info methods (getInstrInfo, +getRegisterInfo, getFrameInfo, etc.). This class is +designed to be specialized by a concrete target implementation (e.g., X86TargetMachine) which implements the various virtual methods. The only required target description class is the TargetData class, but if the @@ -289,13 +343,33 @@ implemented as well.
The TargetData class is the only required target description class, -and it is the only class that is not extensible (it cannot be derived from). It -specifies information about how the target lays out memory for structures, the -alignment requirements for various data types, the size of pointers in the -target, and whether the target is little- or big-endian.
+and it is the only class that is not extensible (you cannot derived a new +class from it). TargetData specifies information about how the target +lays out memory for structures, the alignment requirements for various data +types, the size of pointers in the target, and whether the target is +little-endian or big-endian. + +The TargetLowering class is used by SelectionDAG based instruction +selectors primarily to describe how LLVM code should be lowered to SelectionDAG +operations. Among other things, this class indicates: +
Registers in the code generator are represented in the code generator by unsigned numbers. Physical registers (those that actually exist in the target description) are unique small numbers, and virtual registers are generally -large.
+large. Note that register #0 is reserved as a flag value.Each register in the processor description has an associated -MRegisterDesc entry, which provides a textual name for the register -(used for assembly output and debugging dumps), a set of aliases (used to -indicate that one register overlaps with another), and some flag bits. +TargetRegisterDesc entry, which provides a textual name for the register +(used for assembly output and debugging dumps) and a set of aliases (used to +indicate that one register overlaps with another).
In addition to the per-register description, the MRegisterInfo class @@ -339,11 +413,46 @@ href="TableGenFundamentals.html">TableGen description of the register file. The TargetInstrInfo class
The TargetInstrInfo class is used to describe the machine + instructions supported by the target. It is essentially an array of + TargetInstrDescriptor objects, each of which describes one + instruction the target supports. Descriptors define things like the mnemonic + for the opcode, the number of operands, the list of implicit register uses + and defs, whether the instruction has certain target-independent properties + (accesses memory, is commutable, etc), and holds any target-specific flags.
+The TargetFrameInfo class is used to provide information about the + stack frame layout of the target. It holds the direction of stack growth, + the known stack alignment on entry to each function, and the offset to the + locals area. The offset to the local area is the offset from the stack + pointer on function entry to the first location where function data (local + variables, spill locations) can be stored.
++
The TargetSubtarget class is used to provide information about the + specific chip set being targeted. A sub-target informs code generation of + which instructions are supported, instruction latencies and instruction + execution itinerary; i.e., which processing units are used, in what order, and + for how long. +
+At the high-level, LLVM code is translated to a machine specific representation -formed out of MachineFunction, MachineBasicBlock, and MachineFunction, +MachineBasicBlock, and MachineInstr instances (defined in include/llvm/CodeGen). This representation is completely target agnostic, representing instructions in their most abstract form: an opcode and a @@ -378,14 +488,14 @@ representation for machine code, as well as a register allocated, non-SSA form.
Target machine instructions are represented as instances of the MachineInstr class. This class is an extremely abstract way of -representing machine instructions. In particular, all it keeps track of is -an opcode number and some number of operands.
+representing machine instructions. In particular, it only keeps track of +an opcode number and a set of operands. -The opcode number is an simple unsigned number that only has meaning to a +
The opcode number is a simple unsigned number that only has meaning to a specific backend. All of the instructions for a target should be defined in -the *InstrInfo.td file for the target, and the opcode enum values -are autogenerated from this description. The MachineInstr class does -not have any information about how to intepret the instruction (i.e., what the +the *InstrInfo.td file for the target. The opcode enum values +are auto-generated from this description. The MachineInstr class does +not have any information about how to interpret the instruction (i.e., what the semantics of the instruction are): for that you must refer to the TargetInstrInfo class.
@@ -396,15 +506,15 @@ In addition, a machine operand should be marked as a def or a use of the valueBy convention, the LLVM code generator orders instruction operands so that all register definitions come before the register uses, even on architectures -that are normally printed in other orders. For example, the sparc add +that are normally printed in other orders. For example, the SPARC add instruction: "add %i1, %i2, %i3" adds the "%i1", and "%i2" registers and stores the result into the "%i3" register. In the LLVM code generator, the operands should be stored as "%i3, %i1, %i2": with the destination first.
-Keeping destination operands at the beginning of the operand list has several -advantages. In particular, the debugging printer will print the instruction -like this:
+Keeping destination (definition) operands at the beginning of the operand +list has several advantages. In particular, the debugging printer will print +the instruction like this:
%r3 = add %i1, %i2 @@ -453,17 +563,18 @@ instructions. Usage of the BuildMI functions look like this:The key thing to remember with the BuildMI functions is that you have -to specify the number of operands that the machine instruction will take -(allowing efficient memory allocation). Also, if operands default to be uses -of values, not definitions. If you need to add a definition operand (other -than the optional destination register), you must explicitly mark it as such. +to specify the number of operands that the machine instruction will take. This +allows for efficient memory allocation. You also need to specify if operands +default to be uses of values, not definitions. If you need to add a definition +operand (other than the optional destination register), you must explicitly +mark it as such.
By the end of code generation, the register allocator has coallesced +
By the end of code generation, the register allocator has coalesced the registers and deleted the resultant identity moves, producing the following code:
@@ -533,7 +644,7 @@ register.MachineInstr's are initially instruction selected in SSA-form, and +
MachineInstr's are initially selected in SSA-form, and are maintained in SSA-form until register allocation happens. For the most part, this is trivially simple since LLVM is already in SSA form: LLVM PHI nodes become machine code PHI nodes, and virtual registers are only allowed to have a @@ -544,15 +655,544 @@ are no virtual registers left in the code.
The MachineBasicBlock class contains a list of machine instructions +(MachineInstr instances). It roughly corresponds to +the LLVM code input to the instruction selector, but there can be a one-to-many +mapping (i.e. one LLVM basic block can map to multiple machine basic blocks). +The MachineBasicBlock class has a "getBasicBlock" method, which returns +the LLVM basic block that it comes from. +
+ +The MachineFunction class contains a list of machine basic blocks +(MachineBasicBlock instances). It corresponds +one-to-one with the LLVM function input to the instruction selector. In +addition to a list of basic blocks, the MachineFunction contains a +the MachineConstantPool, MachineFrameInfo, MachineFunctionInfo, +SSARegMap, and a set of live in and live out registers for the function. See +MachineFunction.h for more information. +
+ +This section documents the phases described in the high-level design of the code generator. It +explains how they work and some of the rationale behind their design.
+ ++Instruction Selection is the process of translating LLVM code presented to the +code generator into target-specific machine instructions. There are several +well-known ways to do this in the literature. In LLVM there are two main forms: +the SelectionDAG based instruction selector framework and an old-style 'simple' +instruction selector (which effectively peephole selects each LLVM instruction +into a series of machine instructions). We recommend that all targets use the +SelectionDAG infrastructure. +
+ +Portions of the DAG instruction selector are generated from the target +description files (*.td) files. Eventually, we aim for the entire +instruction selector to be generated from these .td files.
++The SelectionDAG provides an abstraction for code representation in a way that +is amenable to instruction selection using automatic techniques +(e.g. dynamic-programming based optimal pattern matching selectors), It is also +well suited to other phases of code generation; in particular, +instruction scheduling (SelectionDAG's are very close to scheduling DAGs +post-selection). Additionally, the SelectionDAG provides a host representation +where a large variety of very-low-level (but target-independent) +optimizations may be +performed: ones which require extensive information about the instructions +efficiently supported by the target. +
+ ++The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the +SDNode class. The primary payload of the SDNode is its +operation code (Opcode) that indicates what operation the node performs and +the operands to the operation. +The various operation node types are described at the top of the +include/llvm/CodeGen/SelectionDAGNodes.h file.
+ +Although most operations define a single value, each node in the graph may +define multiple values. For example, a combined div/rem operation will define +both the dividend and the remainder. Many other situations require multiple +values as well. Each node also has some number of operands, which are edges +to the node defining the used value. Because nodes may define multiple values, +edges are represented by instances of the SDOperand class, which is +a <SDNode, unsigned> pair, indicating the node and result +value being used, respectively. Each value produced by an SDNode has an +associated MVT::ValueType, indicating what type the value is. +
+ ++SelectionDAGs contain two different kinds of values: those that represent data +flow and those that represent control flow dependencies. Data values are simple +edges with an integer or floating point value type. Control edges are +represented as "chain" edges which are of type MVT::Other. These edges provide +an ordering between nodes that have side effects (such as +loads/stores/calls/return/etc). All nodes that have side effects should take a +token chain as input and produce a new one as output. By convention, token +chain inputs are always operand #0, and chain results are always the last +value produced by an operation.
+ ++A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is +always a marker node with an Opcode of ISD::EntryToken. The Root node is the +final side-effecting node in the token chain. For example, in a single basic +block function, this would be the return node. +
+ ++One important concept for SelectionDAGs is the notion of a "legal" vs. "illegal" +DAG. A legal DAG for a target is one that only uses supported operations and +supported types. On a 32-bit PowerPC, for example, a DAG with any values of i1, +i8, i16, +or i64 type would be illegal, as would a DAG that uses a SREM or UREM operation. +The legalize +phase is responsible for turning an illegal DAG into a legal DAG. +
++SelectionDAG-based instruction selection consists of the following steps: +
+ +After all of these steps are complete, the SelectionDAG is destroyed and the +rest of the code generation passes are run.
+ +One great way to visualize what is going on here is to take advantage of a +few LLC command line options. In particular, the -view-isel-dags +option pops up a window with the SelectionDAG input to the Select phase for all +of the code compiled (if you only get errors printed to the console while using +this, you probably need to configure +your system to add support for it). The -view-sched-dags option +views the SelectionDAG output from the Select phase and input to the Scheduler +phase. +
++The initial SelectionDAG is naively peephole expanded from the LLVM input by +the SelectionDAGLowering class in the SelectionDAGISel.cpp file. The +intent of this pass is to expose as much low-level, target-specific details +to the SelectionDAG as possible. This pass is mostly hard-coded (e.g. an LLVM +add turns into an SDNode add while a geteelementptr is expanded into the obvious +arithmetic). This pass requires target-specific hooks to lower calls and +returns, varargs, etc. For these features, the TargetLowering interface is +used. +
+ +The Legalize phase is in charge of converting a DAG to only use the types and +operations that are natively supported by the target. This involves two major +tasks:
+ +Convert values of unsupported types to values of supported types.
+There are two main ways of doing this: converting small types to + larger types ("promoting"), and breaking up large integer types + into smaller ones ("expanding"). For example, a target might require + that all f32 values are promoted to f64 and that all i1/i8/i16 values + are promoted to i32. The same target might require that all i64 values + be expanded into i32 values. These changes can insert sign and zero + extensions as + needed to make sure that the final code has the same behavior as the + input.
+A target implementation tells the legalizer which types are supported + (and which register class to use for them) by calling the + "addRegisterClass" method in its TargetLowering constructor.
+Eliminate operations that are not supported by the target.
+Targets often have weird constraints, such as not supporting every + operation on every supported datatype (e.g. X86 does not support byte + conditional moves and PowerPC does not support sign-extending loads from + a 16-bit memory location). Legalize takes care by open-coding + another sequence of operations to emulate the operation ("expansion"), by + promoting to a larger type that supports the operation + (promotion), or using a target-specific hook to implement the + legalization (custom).
+A target implementation tells the legalizer which operations are not + supported (and which of the above three actions to take) by calling the + "setOperationAction" method in its TargetLowering constructor.
++Prior to the existance of the Legalize pass, we required that every +target selector supported and handled every +operator and type even if they are not natively supported. The introduction of +the Legalize phase allows all of the +cannonicalization patterns to be shared across targets, and makes it very +easy to optimize the cannonicalized code because it is still in the form of +a DAG. +
+ ++The SelectionDAG optimization phase is run twice for code generation: once +immediately after the DAG is built and once after legalization. The first run +of the pass allows the initial code to be cleaned up (e.g. performing +optimizations that depend on knowing that the operators have restricted type +inputs). The second run of the pass cleans up the messy code generated by the +Legalize pass, which allows Legalize to be very simple (it can focus on making +code legal instead of focusing on generating good and legal code). +
+ ++One important class of optimizations performed is optimizing inserted sign and +zero extension instructions. We currently use ad-hoc techniques, but could move +to more rigorous techniques in the future. Here are some good +papers on the subject:
+ +
+"Widening
+integer arithmetic"
+Kevin Redwine and Norman Ramsey
+International Conference on Compiler Construction (CC) 2004
+
+ "Effective
+ sign extension elimination"
+ Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani
+ Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
+ and Implementation.
+
The Select phase is the bulk of the target-specific code for instruction +selection. This phase takes a legal SelectionDAG as input, +pattern matches the instructions supported by the target to this DAG, and +produces a new DAG of target code. For example, consider the following LLVM +fragment:
+ ++ %t1 = add float %W, %X + %t2 = mul float %t1, %Y + %t3 = add float %t2, %Z ++ +
This LLVM code corresponds to a SelectionDAG that looks basically like this: +
+ ++ (fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z) ++ +
If a target supports floating point multiply-and-add (FMA) operations, one +of the adds can be merged with the multiply. On the PowerPC, for example, the +output of the instruction selector might look like this DAG:
+ ++ (FMADDS (FADDS W, X), Y, Z) ++ +
+The FMADDS instruction is a ternary instruction that multiplies its first two +operands and adds the third (as single-precision floating-point numbers). The +FADDS instruction is a simple binary single-precision add instruction. To +perform this pattern match, the PowerPC backend includes the following +instruction definitions: +
+ ++def FMADDS : AForm_1<59, 29, + (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), + "fmadds $FRT, $FRA, $FRC, $FRB", + [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC), + F4RC:$FRB))]>; +def FADDS : AForm_2<59, 21, + (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB), + "fadds $FRT, $FRA, $FRB", + [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; ++ +
The portion of the instruction definition in bold indicates the pattern used +to match the instruction. The DAG operators (like fmul/fadd) +are defined in the lib/Target/TargetSelectionDAG.td file. +"F4RC" is the register class of the input and result values.
+ +
The TableGen DAG instruction selector generator reads the instruction +patterns in the .td and automatically builds parts of the pattern matching code +for your target. It has the following strengths:
+ ++ // Arbitrary immediate support. Implement in terms of LIS/ORI. + def : Pat<(i32 imm:$imm), + (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; ++ + If none of the single-instruction patterns for loading an immediate into a + register match, this will be used. This rule says "match an arbitrary i32 + immediate, turning it into an ORI ('or a 16-bit immediate') and an LIS + ('load 16-bit immediate, where the immediate is shifted to the left 16 + bits') instruction". To make this work, the LO16/HI16 node transformations + are used to manipulate the input immediate (in this case, take the high or + low 16-bits of the immediate). +
+While it has many strengths, the system currently has some limitations, +primarily because it is a work in progress and is not yet finished: +
+ +Despite these limitations, the instruction selector generator is still quite +useful for most of the binary and logical operations in typical instruction +sets. If you run into any problems or can't figure out how to do something, +please let Chris know!
+ +The scheduling phase takes the DAG of target instructions from the selection +phase and assigns an order. The scheduler can pick an order depending on +various constraints of the machines (i.e. order for minimal register pressure or +try to cover instruction latencies). Once an order is established, the DAG is +converted to a list of MachineInstrs and the +Selection DAG is destroyed. +
+ +Note that this phase is logically separate from the instruction selection +phase, but is tied to it closely in the code because it operates on +SelectionDAGs.
+ +To Be Written
To Be Written
To Be Written
To Be Written
For the JIT or .o file writer
+This section of the document explains any features or design decisions that +
This section of the document explains features or design decisions that are specific to the code generator for a particular target.
+The following are the known target triples that are supported by the X86 +backend. This is not an exhaustive list, but it would be useful to add those +that people test. +
+ +-The x86 has a very, uhm, flexible, way of accessing memory. It is capable of +
The x86 has a very flexible way of accessing memory. It is capable of forming memory addresses of the following expression directly in integer instructions (which use ModR/M addressing):
@@ -591,9 +1252,9 @@ instructions (which use ModR/M addressing): Base+[1,2,4,8]*IndexReg+Disp32 -Wow, that's crazy. In order to represent this, LLVM tracks no less that 4 -operands for each memory operand of this form. This means that the "load" form -of 'mov' has the following "Operands" in this order:
+In order to represent this, LLVM tracks no less than 4 operands for each +memory operand of this form. This means that the "load" form of 'mov' has the +following MachineOperands in this order:
Index: 0 | 1 2 3 4 @@ -601,8 +1262,8 @@ Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm-
Stores and all other instructions treat the four memory operands in the same -way, in the same order.
+Stores, and all other instructions, treat the four memory operands in the +same way, in the same order.
-An instruction name consists of the base name, a default operand size -followed by a character per operand with an optional special size. For -example:
+An instruction name consists of the base name, a default operand size, and a +a character per operand with an optional special size. For example:
ADD8rr -> add, 8-bit register, 8-bit register