X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=docs%2FCodeGenerator.html;h=8b1db7ac3da7ac4ee8f56919658ecb86daed6ada;hb=170f06ebe2e80ce8bda87425081541493056fb10;hp=e620c1782e9923d777634c6eda5e0f3c365a3c79;hpb=1777d0c6c555fb20177b3a60b40eef265c2b842a;p=oota-llvm.git diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html index e620c1782e9..8b1db7ac3da 100644 --- a/docs/CodeGenerator.html +++ b/docs/CodeGenerator.html @@ -86,6 +86,7 @@
-MI.addReg(Reg, MachineOperand::Def); +MI.addReg(Reg, RegState::Define);
-%t1 = add float %W, %X -%t2 = mul float %t1, %Y -%t3 = add float %t2, %Z +%t1 = fadd float %W, %X +%t2 = fmul float %t1, %Y +%t3 = fadd float %t2, %Z
The portion of the instruction definition in bold indicates the pattern used to match the instruction. The DAG operators (like fmul/fadd) are defined in - the lib/Target/TargetSelectionDAG.td file. "F4RC" is the - register class of the input and result values.
+ the include/llvm/Target/TargetSelectionDAG.td file. " + F4RC" is the register class of the input and result values.The TableGen DAG instruction selector generator reads the instruction patterns in the .td file and automatically builds parts of the @@ -1380,9 +1381,9 @@ bool RegMapping_Fer::compatible_class(MachineFunction &mf, for RegisterClass, the last parameter of which is a list of registers. Just commenting some out is one simple way to avoid them being used. A more polite way is to explicitly exclude some registers from - the allocation order. See the definition of the GR register - class in lib/Target/IA64/IA64RegisterInfo.td for an example of this - (e.g., numReservedRegs registers are hidden.)
+ the allocation order. See the definition of the GR8 register + class in lib/Target/X86/X86RegisterInfo.td for an example of this. +Virtual registers are also denoted by integer numbers. Contrary to physical registers, different virtual registers never share the same number. The @@ -1429,7 +1430,7 @@ bool RegMapping_Fer::compatible_class(MachineFunction &mf, instruction, use TargetInstrInfo::get(opcode)::ImplicitUses. Pre-colored registers impose constraints on any register allocation algorithm. The - register allocator must make sure that none of them is been overwritten by + register allocator must make sure that none of them are overwritten by the values of virtual registers while still alive.
@@ -1593,22 +1594,22 @@ bool RegMapping_Fer::compatible_class(MachineFunction &mf, different register allocators:The type of register allocator used in llc can be chosen with the @@ -1616,9 +1617,9 @@ bool RegMapping_Fer::compatible_class(MachineFunction &mf,
-$ llc -f -regalloc=simple file.bc -o sp.s; -$ llc -f -regalloc=local file.bc -o lc.s; -$ llc -f -regalloc=linearscan file.bc -o ln.s; +$ llc -regalloc=linearscan file.bc -o ln.s; +$ llc -regalloc=fast file.bc -o fa.s; +$ llc -regalloc=pbqp file.bc -o pbqp.s;
On x86 and x86-64 one register is reserved for indirect tail calls (e.g via a - function pointer). So there is one less register for integer argument - passing. For x86 this means 2 registers (if inreg parameter - attribute is used) and for x86-64 this means 5 register are used.
+ + + + +Sibling call optimization is a restricted form of tail call optimization. + Unlike tail call optimization described in the previous section, it can be + performed automatically on any tail calls when -tailcallopt option + is not specified.
+ +Sibling call optimization is currently performed on x86/x86-64 when the + following constraints are met:
+ +Example:
++declare i32 @bar(i32, i32) + +define i32 @foo(i32 %a, i32 %b, i32 %c) { +entry: + %0 = tail call i32 @bar(i32 %a, i32 %b) + ret i32 %0 +} ++
-Base + [1,2,4,8] * IndexReg + Disp32 +SegmentReg: Base + [1,2,4,8] * IndexReg + Disp32
In order to represent this, LLVM tracks no less than 4 operands for each +
In order to represent this, LLVM tracks no less than 5 operands for each memory operand of this form. This means that the "load" form of 'mov' has the following MachineOperands in this order:
-Index: 0 | 1 2 3 4 -Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement -OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm +Index: 0 | 1 2 3 4 5 +Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement Segment +OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm PhysReg
Stores, and all other instructions, treat the four memory operands in the - same way and in the same order.
+ same way and in the same order. If the segment register is unspecified + (regno = 0), then no segment override is generated. "Lea" operations do not + have a segment register specified, so they only have 4 operands for their + memory reference. @@ -1838,7 +1884,8 @@ OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImmx86 has the ability to perform loads and stores to different address spaces +
x86 has an experimental feature which provides + the ability to perform loads and stores to different address spaces via the x86 segment registers. A segment override prefix byte on an instruction causes the instruction's memory access to go to the specified segment. LLVM address space 0 is the default address space, which includes @@ -1848,9 +1895,30 @@ OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm address space 257. Other x86 segments have yet to be allocated address space numbers.
-Some operating systems use the FS/GS-segment to implement TLS, so care - should be taken when reading and writing to address space 256/257 on these - platforms.
+While these address spaces may seem similar to TLS via the + thread_local keyword, and often use the same underlying hardware, + there are some fundamental differences.
+ +The thread_local keyword applies to global variables and + specifies that they are to be allocated in thread-local memory. There are + no type qualifiers involved, and these variables can be pointed to with + normal pointers and accessed with normal loads and stores. + The thread_local keyword is target-independent at the LLVM IR + level (though LLVM doesn't yet have implementations of it for some + configurations).
+ +
Special address spaces, in contrast, apply to static types. Every + load and store has a particular address space in its address operand type, + and this is what determines which address space is accessed. + LLVM ignores these special address space qualifiers on global variables, + and does not provide a way to directly allocate storage in them. + At the LLVM IR level, the behavior of these special address spaces depends + in part on the underlying OS or runtime environment, and they are specific + to x86 (and LLVM doesn't yet handle them correctly in some cases).
+ +Some operating systems and runtime environments use (or may in the future + use) the FS/GS-segment registers for various low-level purposes, so care + should be taken when considering them.