X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=docs%2FCodeGenerator.html;h=fbdc294e4a208dc6b2cf2465bb6c416fae16586e;hb=591466baff32bd76aa3329e18092c0c09528f826;hp=2f716a2161a1bd7bcb2c79d8dd967788627fe94b;hpb=d2cb3d2c32b8f53bf94d56fbdd48503ace28df4b;p=oota-llvm.git diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html index 2f716a2161a..fbdc294e4a2 100644 --- a/docs/CodeGenerator.html +++ b/docs/CodeGenerator.html @@ -86,6 +86,7 @@
-%t1 = add float %W, %X -%t2 = mul float %t1, %Y -%t3 = add float %t2, %Z +%t1 = fadd float %W, %X +%t2 = fmul float %t1, %Y +%t3 = fadd float %t2, %Z
The portion of the instruction definition in bold indicates the pattern used to match the instruction. The DAG operators (like fmul/fadd) are defined in - the lib/Target/TargetSelectionDAG.td file. "F4RC" is the - register class of the input and result values.
+ the include/llvm/Target/TargetSelectionDAG.td file. " + F4RC" is the register class of the input and result values.The TableGen DAG instruction selector generator reads the instruction patterns in the .td file and automatically builds parts of the @@ -1429,7 +1430,7 @@ bool RegMapping_Fer::compatible_class(MachineFunction &mf, instruction, use TargetInstrInfo::get(opcode)::ImplicitUses. Pre-colored registers impose constraints on any register allocation algorithm. The - register allocator must make sure that none of them is been overwritten by + register allocator must make sure that none of them are overwritten by the values of virtual registers while still alive.
@@ -1616,9 +1617,9 @@ bool RegMapping_Fer::compatible_class(MachineFunction &mf,-$ llc -f -regalloc=simple file.bc -o sp.s; -$ llc -f -regalloc=local file.bc -o lc.s; -$ llc -f -regalloc=linearscan file.bc -o ln.s; +$ llc -regalloc=simple file.bc -o sp.s; +$ llc -regalloc=local file.bc -o lc.s; +$ llc -regalloc=linearscan file.bc -o ln.s;
On x86 and x86-64 one register is reserved for indirect tail calls (e.g via a - function pointer). So there is one less register for integer argument - passing. For x86 this means 2 registers (if inreg parameter - attribute is used) and for x86-64 this means 5 register are used.
+ + + + +Sibling call optimization is a restricted form of tail call optimization. + Unlike tail call optimization described in the previous section, it can be + performed automatically on any tail calls when -tailcallopt option + is not specified.
+ +Sibling call optimization is currently performed on x86/x86-64 when the + following constraints are met:
+ +Example:
++declare i32 @bar(i32, i32) + +define i32 @foo(i32 %a, i32 %b, i32 %c) { +entry: + %0 = tail call i32 @bar(i32 %a, i32 %b) + ret i32 %0 +} ++
-Base + [1,2,4,8] * IndexReg + Disp32 +SegmentReg: Base + [1,2,4,8] * IndexReg + Disp32
In order to represent this, LLVM tracks no less than 4 operands for each +
In order to represent this, LLVM tracks no less than 5 operands for each memory operand of this form. This means that the "load" form of 'mov' has the following MachineOperands in this order:
-Index: 0 | 1 2 3 4 -Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement -OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm +Index: 0 | 1 2 3 4 5 +Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement Segment +OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm PhysReg
Stores, and all other instructions, treat the four memory operands in the - same way and in the same order.
+ same way and in the same order. If the segment register is unspecified + (regno = 0), then no segment override is generated. "Lea" operations do not + have a segment register specified, so they only have 4 operands for their + memory reference.