X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=docs%2FCodeGenerator.html;h=fbdc294e4a208dc6b2cf2465bb6c416fae16586e;hb=b2b31a6f93f5329c86e41c04ec8c33799d012f9e;hp=f26d0abfad52a493ec0564c9867dee188d7cf0e3;hpb=dc444e9a236c9e5a9a3a5e6da75f29f7000208d3;p=oota-llvm.git diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html index f26d0abfad5..fbdc294e4a2 100644 --- a/docs/CodeGenerator.html +++ b/docs/CodeGenerator.html @@ -1090,8 +1090,8 @@ def FADDS : AForm_2<59, 21,

The portion of the instruction definition in bold indicates the pattern used to match the instruction. The DAG operators (like fmul/fadd) are defined in - the lib/Target/TargetSelectionDAG.td file. "F4RC" is the - register class of the input and result values.

+ the include/llvm/Target/TargetSelectionDAG.td file. " + F4RC" is the register class of the input and result values.

The TableGen DAG instruction selector generator reads the instruction patterns in the .td file and automatically builds parts of the @@ -1430,7 +1430,7 @@ bool RegMapping_Fer::compatible_class(MachineFunction &mf, instruction, use TargetInstrInfo::get(opcode)::ImplicitUses. Pre-colored registers impose constraints on any register allocation algorithm. The - register allocator must make sure that none of them is been overwritten by + register allocator must make sure that none of them are overwritten by the values of virtual registers while still alive.

@@ -1679,7 +1679,8 @@ $ llc -regalloc=linearscan file.bc -o ln.s; supported on x86/x86-64 and PowerPC. It is performed if: