X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=docs%2FCodeGenerator.rst;h=b89d2f426f388a25cb206b4095246ff33d2a8707;hb=ccbfd5b18a79a07229f11af478843eae16ac9b26;hp=cafa93e46a5facf5f204758301c2397d5e45cd60;hpb=91cb694fd7473fc95d0e0b6f5c6bd52818339e02;p=oota-llvm.git diff --git a/docs/CodeGenerator.rst b/docs/CodeGenerator.rst index cafa93e46a5..b89d2f426f3 100644 --- a/docs/CodeGenerator.rst +++ b/docs/CodeGenerator.rst @@ -1,5 +1,3 @@ -.. _code_generator: - ========================================== The LLVM Target-Independent Code Generator ========================================== @@ -17,6 +15,8 @@ The LLVM Target-Independent Code Generator .partial { background-color: #F88017 } .yes { background-color: #0F0; } .yes:before { content: "Y" } + .na { background-color: #6666FF; } + .na:before { content: "N/A" } .. contents:: @@ -285,12 +285,10 @@ The ``TargetInstrInfo`` class ----------------------------- The ``TargetInstrInfo`` class is used to describe the machine instructions -supported by the target. It is essentially an array of ``TargetInstrDescriptor`` -objects, each of which describes one instruction the target -supports. Descriptors define things like the mnemonic for the opcode, the number -of operands, the list of implicit register uses and defs, whether the -instruction has certain target-independent properties (accesses memory, is -commutable, etc), and holds any target-specific flags. +supported by the target. Descriptions define things like the mnemonic for +the opcode, the number of operands, the list of implicit register uses and defs, +whether the instruction has certain target-independent properties (accesses +memory, is commutable, etc), and holds any target-specific flags. The ``TargetFrameInfo`` class ----------------------------- @@ -436,12 +434,12 @@ For example, consider this simple LLVM example: .. code-block:: llvm define i32 @test(i32 %X, i32 %Y) { - %Z = udiv i32 %X, %Y + %Z = sdiv i32 %X, %Y ret i32 %Z } -The X86 instruction selector produces this machine code for the ``div`` and -``ret`` (use "``llc X.bc -march=x86 -print-machineinstrs``" to get this): +The X86 instruction selector might produce this machine code for the ``div`` and +``ret``: .. code-block:: llvm @@ -456,8 +454,8 @@ The X86 instruction selector produces this machine code for the ``div`` and %EAX = mov %reg1026 ;; 32-bit return value goes in EAX ret -By the end of code generation, the register allocator has coalesced the -registers and deleted the resultant identity moves producing the following +By the end of code generation, the register allocator would coalesce the +registers and delete the resultant identity moves producing the following code: .. code-block:: llvm @@ -638,6 +636,18 @@ file (MCObjectStreamer). MCAsmStreamer is a straight-forward implementation that prints out a directive for each method (e.g. ``EmitValue -> .byte``), but MCObjectStreamer implements a full assembler. +For target specific directives, the MCStreamer has a MCTargetStreamer instance. +Each target that needs it defines a class that inherits from it and is a lot +like MCStreamer itself: It has one method per directive and two classes that +inherit from it, a target object streamer and a target asm streamer. The target +asm streamer just prints it (``emitFnStart -> .fnstrart``), and the object +streamer implement the assembler logic for it. + +To make llvm use these classes, the target initialization must call +TargetRegistry::RegisterAsmStreamer and TargetRegistry::RegisterMCObjectStreamer +passing callbacks that allocate the corresponding target streamer and pass it +to createAsmStreamer or to the appropriate object streamer constructor. + The ``MCContext`` class ----------------------- @@ -1040,6 +1050,24 @@ for your target. It has the following strengths: are used to manipulate the input immediate (in this case, take the high or low 16-bits of the immediate). +* When using the 'Pat' class to map a pattern to an instruction that has one + or more complex operands (like e.g. `X86 addressing mode`_), the pattern may + either specify the operand as a whole using a ``ComplexPattern``, or else it + may specify the components of the complex operand separately. The latter is + done e.g. for pre-increment instructions by the PowerPC back end: + + :: + + def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst), + "stwu $rS, $dst", LdStStoreUpd, []>, + RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; + + def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff), + (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>; + + Here, the pair of ``ptroff`` and ``ptrreg`` operands is matched onto the + complex operand ``dst`` of class ``memri`` in the ``STWU`` instruction. + * While the system does automate a lot, it still allows you to write custom C++ code to match special cases if there is something that is hard to express. @@ -1598,7 +1626,7 @@ Implementing a Native Assembler =============================== Though you're probably reading this because you want to write or maintain a -compiler backend, LLVM also fully supports building a native assemblers too. +compiler backend, LLVM also fully supports building a native assembler. We've tried hard to automate the generation of the assembler from the .td files (in particular the instruction syntax and encodings), which means that a large part of the manual and repetitive data entry can be factored and shared with the @@ -1732,6 +1760,8 @@ This section of the document explains features or design decisions that are specific to the code generator for a particular target. First we start with a table that summarizes what features are supported by each target. +.. _target-feature-matrix: + Target Feature Matrix --------------------- @@ -1746,12 +1776,14 @@ the key: :raw-html:`
Unknown | ` +:raw-html:`Not Applicable | ` :raw-html:`No support | ` :raw-html:`Partial Support | ` :raw-html:`Complete Support | ` :raw-html:`|||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
` +:raw-html:` | ` :raw-html:` | ` :raw-html:` | ` :raw-html:` | ` @@ -1768,12 +1800,12 @@ Here is the table: :raw-html:` | Feature | ` :raw-html:`ARM | ` :raw-html:`Hexagon | ` -:raw-html:`MBlaze | ` :raw-html:`MSP430 | ` :raw-html:`Mips | ` -:raw-html:`PTX | ` +:raw-html:`NVPTX | ` :raw-html:`PowerPC | ` :raw-html:`Sparc | ` +:raw-html:`SystemZ | ` :raw-html:`X86 | ` :raw-html:`XCore | ` :raw-html:`is generally reliable | ` :raw-html:`` :raw-html:` | ` -:raw-html:` | ` :raw-html:` | ` :raw-html:` | ` -:raw-html:` | ` +:raw-html:` | ` :raw-html:` | ` :raw-html:` | ` +:raw-html:` | ` :raw-html:` | ` -:raw-html:` | ` +:raw-html:` | ` :raw-html:`` :raw-html:` |
assembly parser | ` :raw-html:`` :raw-html:` | ` -:raw-html:` | ` :raw-html:` | ` :raw-html:` | ` -:raw-html:` | ` +:raw-html:` | ` :raw-html:` | ` :raw-html:` | ` +:raw-html:` | ` :raw-html:` | ` :raw-html:` | ` :raw-html:` | disassembler | ` :raw-html:`` :raw-html:` | ` -:raw-html:` | ` :raw-html:` | ` :raw-html:` | ` -:raw-html:` | ` +:raw-html:` | ` :raw-html:` | ` +:raw-html:` | ` :raw-html:` | ` :raw-html:` | ` -:raw-html:` | ` +:raw-html:` | ` :raw-html:`` :raw-html:` |
inline asm | ` :raw-html:`` :raw-html:` | ` -:raw-html:` | ` :raw-html:` | ` :raw-html:` | ` -:raw-html:` | ` +:raw-html:` | ` :raw-html:` | ` :raw-html:` | ` +:raw-html:` | ` :raw-html:` | ` -:raw-html:` | ` +:raw-html:` | ` :raw-html:` | ||||
jit | ` :raw-html:`* | ` :raw-html:`` -:raw-html:` | ` :raw-html:` | ` :raw-html:` | ` -:raw-html:` | ` +:raw-html:` | ` :raw-html:` | ` :raw-html:` | ` +:raw-html:` | ` :raw-html:` | ` -:raw-html:` | ` +:raw-html:` | ` :raw-html:` | ||||
.o file writing | ` :raw-html:`` :raw-html:` | ` -:raw-html:` | ` :raw-html:` | ` :raw-html:` | ` -:raw-html:` | ` +:raw-html:` | ` :raw-html:` | ` :raw-html:` | ` +:raw-html:` | ` :raw-html:` | ` :raw-html:` | ` :raw-html:` | tail calls | ` :raw-html:`` :raw-html:` | ` -:raw-html:` | ` :raw-html:` | ` :raw-html:` | ` -:raw-html:` | ` +:raw-html:` | ` :raw-html:` | ` :raw-html:` | ` +:raw-html:` | ` :raw-html:` | ` -:raw-html:` | ` +:raw-html:` | ` :raw-html:`` :raw-html:` |
segmented stacks | ` :raw-html:`` :raw-html:` | ` -:raw-html:` | ` :raw-html:` | ` :raw-html:` | ` -:raw-html:` | ` +:raw-html:` | ` :raw-html:` | ` :raw-html:` | ` +:raw-html:` | ` :raw-html:` | * | ` :raw-html:`` :raw-html:` | Description | ` :raw-html:`` :raw-html:`||||
``double`` | ` -:raw-html:`If enabled, the map_f64_to_f32 directive is disabled in the PTX output, allowing native double-precision arithmetic | ` +:raw-html:`sm_20 | ` +:raw-html:`Set shader model/compute capability to 2.0 | ` +:raw-html:`||||||||||||||
sm_21 | ` +:raw-html:`Set shader model/compute capability to 2.1 | ` :raw-html:`||||||||||||||||
``no-fma`` | ` -:raw-html:`Disable generation of Fused-Multiply Add instructions, which may be beneficial for some devices | ` +:raw-html:`sm_30 | ` +:raw-html:`Set shader model/compute capability to 3.0 | ` :raw-html:`||||||||||||||
``smxy / computexy`` | ` -:raw-html:`Set shader model/compute capability to x.y, e.g. sm20 or compute13 | ` +:raw-html:`sm_35 | ` +:raw-html:`Set shader model/compute capability to 3.5 | ` +:raw-html:`||||||||||||||
ptx30 | ` +:raw-html:`Target PTX 3.0 | ` +:raw-html:`||||||||||||||||
ptx31 | ` +:raw-html:`Target PTX 3.1 | ` :raw-html:`