X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=docs%2FCommandGuide%2Fllc.pod;h=f5fd34f01ab51eaa192207c220fcdc92830c5127;hb=95df6b3603e228cea714be21997fec82cb03011e;hp=1f202aab0c9880e8e2b787108f81076992786768;hpb=c8dec2c23e7b31e4f7a40d686d95513a442a0b6e;p=oota-llvm.git diff --git a/docs/CommandGuide/llc.pod b/docs/CommandGuide/llc.pod index 1f202aab0c9..f5fd34f01ab 100644 --- a/docs/CommandGuide/llc.pod +++ b/docs/CommandGuide/llc.pod @@ -10,43 +10,18 @@ B [I] [I] =head1 DESCRIPTION -The B command compiles LLVM bytecode into assembly language for a +The B command compiles LLVM bitcode into assembly language for a specified architecture. The assembly language output can then be passed through -a native assembler and linker to generate native code. +a native assembler and linker to generate a native executable. -The choice of architecture for the output assembly code is determined as -follows, by attempting to satisfy each of the following rules in turn (first -one wins): - -=over - -=item * - -If the user has specified an architecture with the -m option, use that -architecture. - -=item * - -Examine the input LLVM bytecode file: if it is little endian and has a -pointer size of 32 bits, select the Intel IA-32 architecture. If it is big -endian and has a pointer size of 64 bits, select the SparcV9 architecture. - -=item * - -If B was compiled on an architecture for which it can generate code, select -the architecture upon which B was compiled. - -=item * - -Exit with an error message telling the user to specify the output -architecture explicitly. - -=back +The choice of architecture for the output assembly code is automatically +determined from the input bitcode file, unless the B<-march> option is used to +override the default. =head1 OPTIONS -If I is - or omitted, B reads LLVM bytecode from standard input. -Otherwise, it will read LLVM bytecode from I. +If I is - or omitted, B reads LLVM bitcode from standard input. +Otherwise, it will read LLVM bitcode from I. If the B<-o> option is omitted, then B will send its output to standard output if the input is from standard input. If the B<-o> option specifies -, @@ -58,69 +33,91 @@ removing any existing F<.bc> extension, and adding a F<.s> suffix. Other B options are as follows: +=head2 End-user Options + =over +=item B<--help> + +Print a summary of command line options. + =item B<-f> Overwrite output files. By default, B will refuse to overwrite an output file which already exists. +=item B<-mtriple>=I + +Override the target triple specified in the input bitcode file with the +specified string. + =item B<-march>=I -Specify the architecture for which to generate assembly. Valid -architectures are: +Specify the architecture for which to generate assembly, overriding the target +encoded in the bitcode file. See the output of B for a list of +valid architectures. By default this is inferred from the target triple or +autodetected to the current architecture. -=over +=item B<-mcpu>=I -=item I +Specify a specific chip in the current architecture to generate code for. +By default this is inferred from the target triple and autodetected to +the current architecture. For a list of available CPUs, use: +B /dev/null | llc -march=xyz -mcpu=help> -Intel IA-32 (Pentium and above) +=item B<-mattr>=I -=item I +Override or control specific attributes of the target, such as whether SIMD +operations are enabled or not. The default set of attributes is set by the +current CPU. For a list of available attributes, use: +B /dev/null | llc -march=xyz -mattr=help> -64-bit SPARC V9 +=item B<--disable-fp-elim> -=item I +Disable frame pointer elimination optimization. -Emit C code, not assembly +=item B<--disable-excess-fp-precision> -=back +Disable optimizations that may produce excess precision for floating point. +Note that this option can dramatically slow down code on some systems +(e.g. X86). -=item B<-enable-correct-eh-support> +=item B<--enable-unsafe-fp-math> -Instruct the B<-lowerinvoke> pass to insert code for correct exception handling -support. This is expensive and is by default omitted for efficiency. +Enable optimizations that make unsafe assumptions about IEEE math (e.g. that +addition is associative) or may not work for all input ranges. These +optimizations allow the code generator to make use of some instructions which +would otherwise not be usable (such as fsin on X86). -=item B<-help> +=item B<--enable-correct-eh-support> -Print a summary of command line options. +Instruct the B pass to insert code for correct exception handling +support. This is expensive and is by default omitted for efficiency. -=item B<-stats> +=item B<--stats> Print statistics recorded by code-generation passes. -=item B<-time-passes> +=item B<--time-passes> Record the amount of time needed for each pass and print a report to standard error. -=back +=item B<--load>=F -=head2 Intel IA-32-specific Options +Dynamically load F (a path to a dynamically shared object) that +implements an LLVM target. This will permit the target name to be used with the +B<-march> option so that code can be generated for that target. -=over - -=item B<--disable-fp-elim> - -Disable frame pointer elimination optimization. +=back -=item B<--disable-pattern-isel> +=head2 Tuning/Configuration Options -Use the 'simple' X86 instruction selector (the default). +=over =item B<--print-machineinstrs> -Print generated machine code. +Print generated machine code between compilation phases (useful for debugging). =item B<--regalloc>=I @@ -141,6 +138,10 @@ Local register allocator Linear scan global register allocator +=item I + +Iterative scan global register allocator + =back =item B<--spiller>=I @@ -163,26 +164,14 @@ Local spiller =back -=head2 SPARCV9-specific Options +=head2 Intel IA-32-specific Options =over -=item B<--disable-peephole> - -Disable peephole optimization pass. - -=item B<--disable-sched> - -Disable local scheduling pass. - -=item B<--disable-strip> - -The Sparc backend embeds the LLVM bytecode into the assembly output. This -option requests that symbol names be retained; by default, they are stripped out. - -=item B<--enable-maps> +=item B<--x86-asm-syntax=att|intel> -Emit LLVM-to-machine code mapping information into the assembly output. +Specify whether to emit assembly code in AT&T syntax (the default) or intel +syntax. =back @@ -197,6 +186,6 @@ L =head1 AUTHORS -Maintained by the LLVM Team (L). +Maintained by the LLVM Team (L). =cut