X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=docs%2FTableGenFundamentals.html;h=ade4bf67df5974439b51ce52f32b5aa624d37175;hb=9e6d1d1f5034347d237941f1bf08fba5c1583cd3;hp=ee1d5b1fe015f1fe45ba74362298506426f3e3cc;hpb=643eb5d7bab77e6fbf10778cfbe2cac2bf5c0aef;p=oota-llvm.git diff --git a/docs/TableGenFundamentals.html b/docs/TableGenFundamentals.html index ee1d5b1fe01..ade4bf67df5 100644 --- a/docs/TableGenFundamentals.html +++ b/docs/TableGenFundamentals.html @@ -104,8 +104,10 @@ definition, so the backend can find all definitions of a particular class, such as "Instruction".
TableGen multiclasses are groups of abstract records that are -instantiated all at once. Each instantiation can result in multiple TableGen -definitions.
+instantiated all at once. Each instantiation can result in multiple +TableGen definitions. If a multiclass inherits from another multiclass, +the definitions in the sub-multiclass become part of the current +multiclass, as if they were declared in the current multiclass. @@ -138,7 +140,7 @@ file prints this (at the time of this writing): bit isIndirectBranch = 0; bit isBarrier = 0; bit isCall = 0; - bit isSimpleLoad = 0; + bit canFoldAsLoad = 0; bit mayLoad = 0; bit mayStore = 0; bit isImplicitDef = 0; @@ -149,7 +151,7 @@ file prints this (at the time of this writing): bit isReMaterializable = 0; bit isPredicable = 0; bit hasDelaySlot = 0; - bit usesCustomDAGSchedInserter = 0; + bit usesCustomInserter = 0; bit hasCtrlDep = 0; bit isNotDuplicable = 0; bit hasSideEffects = 0; @@ -301,43 +303,40 @@ and very high-level types (such as dag). This flexibility is what allows it to describe a wide range of information conveniently and compactly. The TableGen types are: -To date, these types have been sufficient for describing things that TableGen has been used for, but it is straight-forward to extend this list if @@ -357,51 +356,74 @@ when building up values. These forms allow the TableGen file to be written in a natural syntax and flavor for the application. The current expression forms supported include:
-Note that all of the values have rules specifying how they convert to values for different types. These rules allow you to assign a value like "7" @@ -630,8 +652,10 @@ Here is an example TableGen fragment that shows this idea:
The name of the resultant definitions has the multidef fragment names appended to them, so this defines ADD_rr, ADD_ri, - SUB_rr, etc. Using a multiclass this way is exactly equivalent to - instantiating the classes multiple times yourself, e.g. by writing:
+ SUB_rr, etc. A defm may inherit from multiple multiclasses, + instantiating definitions from each multiclass. Using a multiclass + this way is exactly equivalent to instantiating the classes multiple + times yourself, e.g. by writing:@@ -699,7 +723,7 @@ File-scope let expressions are really just another way that TableGen allows the end-user to factor out commonality from the records.File-scope "let" expressions take a comma-separated list of bindings to -apply, and one of more records to bind the values in. Here are some +apply, and one or more records to bind the values in. Here are some examples:
@@ -712,12 +736,12 @@ examples: let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, EFLAGS] in { - def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops), - "call\t${dst:call}", []>; - def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops), - "call\t{*}$dst", [(X86call GR32:$dst)]>; - def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops), - "call\t{*}$dst", []>; + def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops), + "call\t${dst:call}", []>; + def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops), + "call\t{*}$dst", [(X86call GR32:$dst)]>; + def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops), + "call\t{*}$dst", []>; }@@ -728,6 +752,25 @@ opened, as in the case with the CALL* instructions above.
Expressions used by code generator to describe instructions and isel +patterns:
+ +