X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=drivers%2Fvideo%2Frockchip%2Frga%2Frga_reg_info.c;h=b7bbf1d21f74b971c4e2a3c79170d5f43199adf3;hb=089c13477b5bed0c83ebb4e7092f254b70df080d;hp=055827e557528ad1b0a2f63b45f29ed88badf426;hpb=2b57125c3dbc3aad4aded093868c196d8c86ac89;p=firefly-linux-kernel-4.4.55.git diff --git a/drivers/video/rockchip/rga/rga_reg_info.c b/drivers/video/rockchip/rga/rga_reg_info.c index 055827e55752..b7bbf1d21f74 100755 --- a/drivers/video/rockchip/rga/rga_reg_info.c +++ b/drivers/video/rockchip/rga/rga_reg_info.c @@ -15,8 +15,8 @@ #include #include #include -#include -#include +//#include +//#include #include #include #include @@ -36,15 +36,15 @@ #include "rga.h" -/************************************************************* -Func: - RGA_pixel_width_init -Description: - select pixel_width form data format -Author: - ZhangShengqin -Date: - 20012-2-2 10:59:25 +/************************************************************* +Func: + RGA_pixel_width_init +Description: + select pixel_width form data format +Author: + ZhangShengqin +Date: + 20012-2-2 10:59:25 **************************************************************/ unsigned char RGA_pixel_width_init(unsigned int format) @@ -65,7 +65,7 @@ RGA_pixel_width_init(unsigned int format) case RK_FORMAT_RGBA_4444 : pixel_width = 2; break; case RK_FORMAT_BGR_888 : pixel_width = 3; break; - /* YUV FORMAT */ + /* YUV FORMAT */ case RK_FORMAT_YCbCr_422_SP : pixel_width = 1; break; case RK_FORMAT_YCbCr_422_P : pixel_width = 1; break; case RK_FORMAT_YCbCr_420_SP : pixel_width = 1; break; @@ -80,16 +80,16 @@ RGA_pixel_width_init(unsigned int format) return pixel_width; } -/************************************************************* -Func: - dst_ctrl_cal -Description: - calculate dst act window position / width / height - and set the tile struct -Author: - ZhangShengqin -Date: - 20012-2-2 10:59:25 +/************************************************************* +Func: + dst_ctrl_cal +Description: + calculate dst act window position / width / height + and set the tile struct +Author: + ZhangShengqin +Date: + 20012-2-2 10:59:25 **************************************************************/ void dst_ctrl_cal(const struct rga_req *msg, TILE_INFO *tile) @@ -115,10 +115,10 @@ dst_ctrl_cal(const struct rga_req *msg, TILE_INFO *tile) { pos[0] = xoff; pos[1] = yoff; - + pos[2] = xoff; pos[3] = yoff + height - 1; - + pos[4] = xoff + width - 1; pos[5] = yoff + height - 1; @@ -127,16 +127,16 @@ dst_ctrl_cal(const struct rga_req *msg, TILE_INFO *tile) xmax = MIN(MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmax); xmin = MAX(MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmin); - + ymax = MIN(MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymax); ymin = MAX(MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymin); - + //printk("xmax = %d, xmin = %d, ymin = %d, ymax = %d\n", xmax, xmin, ymin, ymax); } else if(msg->rotate_mode == 1) { if((sina == 0) || (cosa == 0)) - { + { if((sina == 0) && (cosa == -65536)) { /* 180 */ @@ -180,7 +180,7 @@ dst_ctrl_cal(const struct rga_req *msg, TILE_INFO *tile) pos[5] = yoff; pos[6] = xoff + height - 1; - pos[7] = yoff - width + 1; + pos[7] = yoff - width + 1; } else { @@ -200,10 +200,10 @@ dst_ctrl_cal(const struct rga_req *msg, TILE_INFO *tile) xmax = MIN(MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmax); xmin = MAX(MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmin); - + ymax = MIN(MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymax); ymin = MAX(MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymin); - } + } else { xx = msg->cosa; @@ -219,7 +219,7 @@ dst_ctrl_cal(const struct rga_req *msg, TILE_INFO *tile) x2 = width + xoff; y2 = height + yoff; - + pos[0] = xoff; pos[1] = yoff; @@ -246,19 +246,19 @@ dst_ctrl_cal(const struct rga_req *msg, TILE_INFO *tile) //printk("xmin = %d, xmax = %d, ymin = %d, ymax = %d\n", xmin, xmax, ymin, ymax); } - } - - if ((xmax < xmin) || (ymax < ymin)) { + } + + if ((xmax < xmin) || (ymax < ymin)) { xmin = xmax; ymin = ymax; - } - - if ((xmin >= msg->dst.vir_w)||(xmax < 0)||(ymin >= msg->dst.vir_h)||(ymax < 0)) { + } + + if ((xmin >= msg->dst.vir_w)||(xmax < 0)||(ymin >= msg->dst.vir_h)||(ymax < 0)) { xmin = xmax = ymin = ymax = 0; } //printk("xmin = %d, xmax = %d, ymin = %d, ymax = %d\n", xmin, xmax, ymin, ymax); - + tile->dst_ctrl.w = (xmax - xmin); tile->dst_ctrl.h = (ymax - ymin); tile->dst_ctrl.x_off = xmin; @@ -273,23 +273,23 @@ dst_ctrl_cal(const struct rga_req *msg, TILE_INFO *tile) tile->dst_y_tmp = ymin - msg->dst.y_offset; } -/************************************************************* -Func: - src_tile_info_cal -Description: - calculate src remap window position / width / height - and set the tile struct -Author: - ZhangShengqin -Date: - 20012-2-2 10:59:25 +/************************************************************* +Func: + src_tile_info_cal +Description: + calculate src remap window position / width / height + and set the tile struct +Author: + ZhangShengqin +Date: + 20012-2-2 10:59:25 **************************************************************/ void src_tile_info_cal(const struct rga_req *msg, TILE_INFO *tile) { - s32 x0, x1, x2, x3, y0, y1, y2, y3; - + s32 x0, x1, x2, x3, y0, y1, y2, y3; + int64_t xx, xy, yx, yy; int64_t pos[8]; @@ -307,10 +307,10 @@ src_tile_info_cal(const struct rga_req *msg, TILE_INFO *tile) yy = tile->matrix[3]; /* 32.32 */ if(msg->rotate_mode == 1) - { + { x0 = tile->dst_x_tmp; y0 = tile->dst_y_tmp; - + x1 = x0; y1 = y0 + 8; @@ -319,8 +319,8 @@ src_tile_info_cal(const struct rga_req *msg, TILE_INFO *tile) x3 = x0 + 8; y3 = y0; - - pos[0] = (x0*xx + y0*yx); + + pos[0] = (x0*xx + y0*yx); pos[1] = (x0*xy + y0*yy); pos[2] = (x1*xx + y1*yx); @@ -355,31 +355,31 @@ src_tile_info_cal(const struct rga_req *msg, TILE_INFO *tile) y_dx = pos[2] - pos[0]; y_dy = pos[3] - pos[1]; - tile->x_dx = (s32)(x_dx >> 22 ); - tile->x_dy = (s32)(x_dy >> 22 ); - tile->y_dx = (s32)(y_dx >> 22 ); - tile->y_dy = (s32)(y_dy >> 22 ); - + tile->x_dx = (s32)(x_dx >> 22 ); + tile->x_dy = (s32)(x_dy >> 22 ); + tile->y_dx = (s32)(y_dx >> 22 ); + tile->y_dy = (s32)(y_dy >> 22 ); + x_temp_start = x0*xx + y0*yx; y_temp_start = x0*xy + y0*yy; - - xmax = (MAX(MAX(MAX(epos[0], epos[2]), epos[4]), epos[6])); - xmin = (MIN(MIN(MIN(epos[0], epos[2]), epos[4]), epos[6])); + + xmax = (MAX(MAX(MAX(epos[0], epos[2]), epos[4]), epos[6])); + xmin = (MIN(MIN(MIN(epos[0], epos[2]), epos[4]), epos[6])); ymax = (MAX(MAX(MAX(epos[1], epos[3]), epos[5]), epos[7])); ymin = (MIN(MIN(MIN(epos[1], epos[3]), epos[5]), epos[7])); t_xoff = (x_temp_start - xmin)>>18; t_yoff = (y_temp_start - ymin)>>18; - + tile->tile_xoff = (s32)t_xoff; tile->tile_yoff = (s32)t_yoff; - + tile->tile_w = (u16)((xmax - xmin)>>21); //.11 tile->tile_h = (u16)((ymax - ymin)>>21); //.11 tile->tile_start_x_coor = (s16)(xmin>>29); //.3 - tile->tile_start_y_coor = (s16)(ymin>>29); //.3 + tile->tile_start_y_coor = (s16)(ymin>>29); //.3 } else if (msg->rotate_mode == 2) { @@ -387,7 +387,7 @@ src_tile_info_cal(const struct rga_req *msg, TILE_INFO *tile) tile->x_dy = 0; tile->y_dx = 0; tile->y_dy = (s32)((8*yy)>>22); - + tile->tile_w = ABS((s32)((7*xx)>>21)); tile->tile_h = ABS((s32)((7*yy)>>21)); @@ -395,7 +395,7 @@ src_tile_info_cal(const struct rga_req *msg, TILE_INFO *tile) tile->tile_yoff = 0; tile->tile_start_x_coor = (((msg->src.act_w - 1)<<11) - (tile->tile_w))>>8; - tile->tile_start_y_coor = 0; + tile->tile_start_y_coor = 0; } else if (msg->rotate_mode == 3) { @@ -403,7 +403,7 @@ src_tile_info_cal(const struct rga_req *msg, TILE_INFO *tile) tile->x_dy = 0; tile->y_dx = 0; tile->y_dy = (s32)((8*yy)>>22); - + tile->tile_w = ABS((s32)((7*xx)>>21)); tile->tile_h = ABS((s32)((7*yy)>>21)); @@ -412,7 +412,7 @@ src_tile_info_cal(const struct rga_req *msg, TILE_INFO *tile) tile->tile_start_x_coor = 0; tile->tile_start_y_coor = (((msg->src.act_h - 1)<<11) - (tile->tile_h))>>8; - } + } if ((msg->scale_mode == 2)||(msg->alpha_rop_flag >> 7)) { @@ -426,23 +426,23 @@ src_tile_info_cal(const struct rga_req *msg, TILE_INFO *tile) } -/************************************************************* -Func: - RGA_set_mode_ctrl -Description: - fill mode ctrl reg info -Author: - ZhangShengqin -Date: - 20012-2-2 10:59:25 +/************************************************************* +Func: + RGA_set_mode_ctrl +Description: + fill mode ctrl reg info +Author: + ZhangShengqin +Date: + 20012-2-2 10:59:25 **************************************************************/ -void +void RGA_set_mode_ctrl(u8 *base, const struct rga_req *msg) { u32 *bRGA_MODE_CTL; u32 reg = 0; - + u8 src_rgb_pack = 0; u8 src_format = 0; u8 src_rb_swp = 0; @@ -453,13 +453,13 @@ RGA_set_mode_ctrl(u8 *base, const struct rga_req *msg) u8 dst_format = 0; u8 dst_rb_swp = 0; u8 dst_a_swp = 0; - + bRGA_MODE_CTL = (u32 *)(base + RGA_MODE_CTRL_OFFSET); - - reg = ((reg & (~m_RGA_MODE_CTRL_2D_RENDER_MODE)) | (s_RGA_MODE_CTRL_2D_RENDER_MODE(msg->render_mode))); + + reg = ((reg & (~m_RGA_MODE_CTRL_2D_RENDER_MODE)) | (s_RGA_MODE_CTRL_2D_RENDER_MODE(msg->render_mode))); /* src info set */ - + if (msg->render_mode == color_palette_mode || msg->render_mode == update_palette_table_mode) { src_format = 0x10 | (msg->palette_mode & 3); @@ -468,37 +468,37 @@ RGA_set_mode_ctrl(u8 *base, const struct rga_req *msg) { switch (msg->src.format) { - case RK_FORMAT_RGBA_8888 : src_format = 0x0; break; - case RK_FORMAT_RGBA_4444 : src_format = 0x3; break; - case RK_FORMAT_RGBA_5551 : src_format = 0x2; break; - case RK_FORMAT_BGRA_8888 : src_format = 0x0; src_rb_swp = 0x1; break; - case RK_FORMAT_RGBX_8888 : src_format = 0x0; break; + case RK_FORMAT_RGBA_8888 : src_format = 0x0; break; + case RK_FORMAT_RGBA_4444 : src_format = 0x3; break; + case RK_FORMAT_RGBA_5551 : src_format = 0x2; break; + case RK_FORMAT_BGRA_8888 : src_format = 0x0; src_rb_swp = 0x1; break; + case RK_FORMAT_RGBX_8888 : src_format = 0x0; break; case RK_FORMAT_RGB_565 : src_format = 0x1; break; case RK_FORMAT_RGB_888 : src_format = 0x0; src_rgb_pack = 1; break; case RK_FORMAT_BGR_888 : src_format = 0x0; src_rgb_pack = 1; src_rb_swp = 1; break; - - case RK_FORMAT_YCbCr_422_SP : src_format = 0x4; break; - case RK_FORMAT_YCbCr_422_P : src_format = 0x5; break; - case RK_FORMAT_YCbCr_420_SP : src_format = 0x6; break; + + case RK_FORMAT_YCbCr_422_SP : src_format = 0x4; break; + case RK_FORMAT_YCbCr_422_P : src_format = 0x5; break; + case RK_FORMAT_YCbCr_420_SP : src_format = 0x6; break; case RK_FORMAT_YCbCr_420_P : src_format = 0x7; break; - case RK_FORMAT_YCrCb_422_SP : src_format = 0x4; src_cbcr_swp = 1; break; - case RK_FORMAT_YCrCb_422_P : src_format = 0x5; src_cbcr_swp = 1; break; - case RK_FORMAT_YCrCb_420_SP : src_format = 0x6; src_cbcr_swp = 1; break; + case RK_FORMAT_YCrCb_422_SP : src_format = 0x4; src_cbcr_swp = 1; break; + case RK_FORMAT_YCrCb_422_P : src_format = 0x5; src_cbcr_swp = 1; break; + case RK_FORMAT_YCrCb_420_SP : src_format = 0x6; src_cbcr_swp = 1; break; case RK_FORMAT_YCrCb_420_P : src_format = 0x7; src_cbcr_swp = 1; break; - } + } } src_a_swp = msg->src.alpha_swap & 1; - reg = ((reg & (~m_RGA_MODE_CTRL_SRC_RGB_PACK)) | (s_RGA_MODE_CTRL_SRC_RGB_PACK(src_rgb_pack))); + reg = ((reg & (~m_RGA_MODE_CTRL_SRC_RGB_PACK)) | (s_RGA_MODE_CTRL_SRC_RGB_PACK(src_rgb_pack))); reg = ((reg & (~m_RGA_MODE_CTRL_SRC_FORMAT)) | (s_RGA_MODE_CTRL_SRC_FORMAT(src_format))); reg = ((reg & (~m_RGA_MODE_CTRL_SRC_RB_SWAP)) | (s_RGA_MODE_CTRL_SRC_RB_SWAP(src_rb_swp))); reg = ((reg & (~m_RGA_MODE_CTRL_SRC_ALPHA_SWAP)) | (s_RGA_MODE_CTRL_SRC_ALPHA_SWAP(src_a_swp))); reg = ((reg & (~m_RGA_MODE_CTRL_SRC_UV_SWAP_MODE )) | (s_RGA_MODE_CTRL_SRC_UV_SWAP_MODE (src_cbcr_swp))); - - - /* YUV2RGB MODE */ + + + /* YUV2RGB MODE */ reg = ((reg & (~m_RGA_MODE_CTRL_YUV2RGB_CON_MODE)) | (s_RGA_MODE_CTRL_YUV2RGB_CON_MODE(msg->yuv2rgb_mode))); /* ROTATE MODE */ @@ -510,7 +510,7 @@ RGA_set_mode_ctrl(u8 *base, const struct rga_req *msg) /* COLOR FILL MODE */ reg = ((reg & (~m_RGA_MODE_CTRL_PAT_SEL)) | (s_RGA_MODE_CTRL_PAT_SEL(msg->color_fill_mode))); - + if ((msg->render_mode == update_palette_table_mode)||(msg->render_mode == update_patten_buff_mode)) { dst_format = msg->pat.format; @@ -519,8 +519,8 @@ RGA_set_mode_ctrl(u8 *base, const struct rga_req *msg) { dst_format = (u8)msg->dst.format; } - - /* dst info set */ + + /* dst info set */ switch (dst_format) { case RK_FORMAT_BGRA_8888 : dst_format = 0x0; dst_rb_swp = 0x1; break; @@ -534,36 +534,36 @@ RGA_set_mode_ctrl(u8 *base, const struct rga_req *msg) } dst_a_swp = msg->dst.alpha_swap & 1; - - reg = ((reg & (~m_RGA_MODE_CTRL_DST_FORMAT)) | (s_RGA_MODE_CTRL_DST_FORMAT(dst_format))); + + reg = ((reg & (~m_RGA_MODE_CTRL_DST_FORMAT)) | (s_RGA_MODE_CTRL_DST_FORMAT(dst_format))); reg = ((reg & (~m_RGA_MODE_CTRL_DST_RGB_PACK)) | (s_RGA_MODE_CTRL_DST_RGB_PACK(dst_rgb_pack))); reg = ((reg & (~m_RGA_MODE_CTRL_DST_RB_SWAP)) | (s_RGA_MODE_CTRL_DST_RB_SWAP(dst_rb_swp))); reg = ((reg & (~m_RGA_MODE_CTRL_DST_ALPHA_SWAP)) | (s_RGA_MODE_CTRL_DST_ALPHA_SWAP(dst_a_swp))); - reg = ((reg & (~m_RGA_MODE_CTRL_LUT_ENDIAN_MODE)) | (s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(msg->endian_mode & 1))); + reg = ((reg & (~m_RGA_MODE_CTRL_LUT_ENDIAN_MODE)) | (s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(msg->endian_mode & 1))); reg = ((reg & (~m_RGA_MODE_CTRL_SRC_TRANS_MODE)) | (s_RGA_MODE_CTRL_SRC_TRANS_MODE(msg->src_trans_mode))); reg = ((reg & (~m_RGA_MODE_CTRL_ZERO_MODE_ENABLE)) | (s_RGA_MODE_CTRL_ZERO_MODE_ENABLE(msg->alpha_rop_mode >> 4))); reg = ((reg & (~m_RGA_MODE_CTRL_DST_ALPHA_ENABLE)) | (s_RGA_MODE_CTRL_DST_ALPHA_ENABLE(msg->alpha_rop_mode >> 5))); *bRGA_MODE_CTL = reg; - + } -/************************************************************* -Func: - RGA_set_src -Description: - fill src relate reg info -Author: - ZhangShengqin -Date: - 20012-2-2 10:59:25 +/************************************************************* +Func: + RGA_set_src +Description: + fill src relate reg info +Author: + ZhangShengqin +Date: + 20012-2-2 10:59:25 **************************************************************/ void RGA_set_src(u8 *base, const struct rga_req *msg) -{ +{ u32 *bRGA_SRC_VIR_INFO; u32 *bRGA_SRC_ACT_INFO; u32 *bRGA_SRC_Y_MST; @@ -575,7 +575,7 @@ RGA_set_src(u8 *base, const struct rga_req *msg) u32 pixel_width; uv_x_off = uv_y_off = uv_stride = 0; - + bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET); bRGA_SRC_CB_MST = (u32 *)(base + RGA_SRC_CB_MST_OFFSET); bRGA_SRC_CR_MST = (u32 *)(base + RGA_SRC_CR_MST_OFFSET); @@ -586,15 +586,15 @@ RGA_set_src(u8 *base, const struct rga_req *msg) y_off = msg->src.y_offset; pixel_width = RGA_pixel_width_init(msg->src.format); - + stride = ((msg->src.vir_w * pixel_width) + 3) & (~3); switch(msg->src.format) { - case RK_FORMAT_YCbCr_422_SP : - uv_stride = stride; - uv_x_off = x_off; - uv_y_off = y_off; + case RK_FORMAT_YCbCr_422_SP : + uv_stride = stride; + uv_x_off = x_off; + uv_y_off = y_off; break; case RK_FORMAT_YCbCr_422_P : uv_stride = stride >> 1; @@ -630,11 +630,11 @@ RGA_set_src(u8 *base, const struct rga_req *msg) uv_stride = stride >> 1; uv_x_off = x_off >> 1; uv_y_off = y_off >> 1; - break; - } + break; + } - /* src addr set */ + /* src addr set */ *bRGA_SRC_Y_MST = msg->src.yrgb_addr + (y_off * stride) + (x_off * pixel_width); *bRGA_SRC_CB_MST = msg->src.uv_addr + uv_y_off * uv_stride + uv_x_off; *bRGA_SRC_CR_MST = msg->src.v_addr + uv_y_off * uv_stride + uv_x_off; @@ -651,32 +651,35 @@ RGA_set_src(u8 *base, const struct rga_req *msg) byte_num = sw >> shift; stride = (byte_num + 3) & (~3); - } + } - /* src act window / vir window set */ + /* src act window / vir window set */ *bRGA_SRC_VIR_INFO = ((stride >> 2) | (msg->src.vir_h)<<16); *bRGA_SRC_ACT_INFO = ((msg->src.act_w-1) | (msg->src.act_h-1)<<16); } -/************************************************************* -Func: - RGA_set_dst -Description: - fill dst relate reg info -Author: - ZhangShengqin -Date: - 20012-2-2 10:59:25 +/************************************************************* +Func: + RGA_set_dst +Description: + fill dst relate reg info +Author: + ZhangShengqin +Date: + 20012-2-2 10:59:25 **************************************************************/ s32 RGA_set_dst(u8 *base, const struct rga_req *msg) { u32 *bRGA_DST_MST; + u32 *bRGA_DST_UV_MST; u32 *bRGA_DST_VIR_INFO; u32 *bRGA_DST_CTR_INFO; u32 *bRGA_PRESCL_CB_MST; u32 *bRGA_PRESCL_CR_MST; + u32 *bRGA_YUV_OUT_CFG; + u32 reg = 0; u8 pw; @@ -685,10 +688,12 @@ s32 RGA_set_dst(u8 *base, const struct rga_req *msg) u16 stride, rop_mask_stride; bRGA_DST_MST = (u32 *)(base + RGA_DST_MST_OFFSET); + bRGA_DST_UV_MST = (u32 *)(base + RGA_DST_UV_MST_OFFSET); bRGA_DST_VIR_INFO = (u32 *)(base + RGA_DST_VIR_INFO_OFFSET); bRGA_DST_CTR_INFO = (u32 *)(base + RGA_DST_CTR_INFO_OFFSET); bRGA_PRESCL_CB_MST = (u32 *)(base + RGA_PRESCL_CB_MST_OFFSET); bRGA_PRESCL_CR_MST = (u32 *)(base + RGA_PRESCL_CR_MST_OFFSET); + bRGA_YUV_OUT_CFG = (u32 *)(base + RGA_YUV_OUT_CFG_OFFSET); pw = RGA_pixel_width_init(msg->dst.format); @@ -696,72 +701,84 @@ s32 RGA_set_dst(u8 *base, const struct rga_req *msg) *bRGA_DST_MST = (u32)msg->dst.yrgb_addr + (y_off * stride) + (x_off * pw); - if (msg->render_mode == pre_scaling_mode) + *bRGA_DST_UV_MST = 0; + *bRGA_YUV_OUT_CFG = 0; + switch(msg->dst.format) { - switch(msg->dst.format) - { - case RK_FORMAT_YCbCr_422_SP : - *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw); - break; - case RK_FORMAT_YCbCr_422_P : - *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw); - *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off) * stride) + ((x_off>>1) * pw); - break; - case RK_FORMAT_YCbCr_420_SP : - *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw); - break; - case RK_FORMAT_YCbCr_420_P : - *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw); - *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw); - break; - case RK_FORMAT_YCrCb_422_SP : - *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw); - break; - case RK_FORMAT_YCrCb_422_P : - *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw); - *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off) * stride) + ((x_off>>1) * pw); - break; - case RK_FORMAT_YCrCb_420_SP : - *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw); - break; - case RK_FORMAT_YCrCb_420_P : - *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw); - *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw); - break; - } + case RK_FORMAT_YCbCr_422_SP : + *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw); + *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off)); + *bRGA_YUV_OUT_CFG |= (0 << 3) | 1 | (((msg->yuv2rgb_mode >> 4) & 3) << 4); + break; + case RK_FORMAT_YCbCr_422_P : + *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw); + *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off) * stride) + ((x_off>>1) * pw); + break; + case RK_FORMAT_YCbCr_420_SP : + *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw); + *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off)); + *bRGA_YUV_OUT_CFG |= (0 << 3)|(1 << 1) | 1 | (((msg->yuv2rgb_mode >> 4) & 3) << 4); + break; + case RK_FORMAT_YCbCr_420_P : + *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw); + *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw); + break; + case RK_FORMAT_YCrCb_422_SP : + *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw); + *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off)); + *bRGA_YUV_OUT_CFG |= (1 << 3)|(0 << 1) | 1 | (((msg->yuv2rgb_mode >> 4) & 3) << 4); + break; + case RK_FORMAT_YCrCb_422_P : + *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw); + *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off) * stride) + ((x_off>>1) * pw); + break; + case RK_FORMAT_YCrCb_420_SP : + *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw); + *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off)); + *bRGA_YUV_OUT_CFG |= (1 << 3)|(1 << 1) | 1 | (((msg->yuv2rgb_mode >> 4) & 3) << 4); + break; + case RK_FORMAT_YCrCb_420_P : + *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw); + *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw); + break; } rop_mask_stride = (((msg->src.vir_w + 7)>>3) + 3) & (~3);//not dst_vir.w,hxx,2011.7.21 - + reg = (stride >> 2) & 0xffff; reg = reg | ((rop_mask_stride>>2) << 16); - #if defined(CONFIG_ARCH_RK2928) - reg = reg | ((msg->alpha_rop_mode & 3) << 28); + #if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3188) + //reg = reg | ((msg->alpha_rop_mode & 3) << 28); + reg = reg | (1 << 28); #endif if (msg->render_mode == line_point_drawing_mode) { reg &= 0xffff; - reg = reg | (msg->dst.vir_h << 16); + reg = reg | (msg->dst.vir_h << 16); } *bRGA_DST_VIR_INFO = reg; *bRGA_DST_CTR_INFO = (msg->dst.act_w - 1) | ((msg->dst.act_h - 1) << 16); - return 0; + if (msg->render_mode == pre_scaling_mode) { + *bRGA_YUV_OUT_CFG &= 0xfffffffe; + } + + return 0; } -/************************************************************* -Func: - RGA_set_alpha_rop -Description: - fill alpha rop some relate reg bit -Author: - ZhangShengqin -Date: - 20012-2-2 10:59:25 +/************************************************************* +Func: + RGA_set_alpha_rop +Description: + fill alpha rop some relate reg bit +Author: + ZhangShengqin +Date: + 20012-2-2 10:59:25 **************************************************************/ void RGA_set_alpha_rop(u8 *base, const struct rga_req *msg) @@ -771,12 +788,12 @@ RGA_set_alpha_rop(u8 *base, const struct rga_req *msg) u32 *bRGA_ROP_CON1; u32 reg = 0; u32 rop_con0, rop_con1; - + u8 rop_mode = (msg->alpha_rop_mode) & 3; u8 alpha_mode = msg->alpha_rop_mode & 3; rop_con0 = rop_con1 = 0; - + bRGA_ALPHA_CON = (u32 *)(base + RGA_ALPHA_CON_OFFSET); reg = ((reg & (~m_RGA_ALPHA_CON_ENABLE) )| (s_RGA_ALPHA_CON_ENABLE(msg->alpha_rop_flag & 1))); @@ -791,10 +808,10 @@ RGA_set_alpha_rop(u8 *base, const struct rga_req *msg) reg = ((reg & (~m_RGA_ALPHA_CON_DITHER_ENABLE)) | (s_RGA_ALPHA_CON_DITHER_ENABLE(msg->alpha_rop_flag >> 5))); reg = ((reg & (~m_RGA_ALPHA_CON_GRADIENT_CAL_MODE)) | (s_RGA_ALPHA_CON_GRADIENT_CAL_MODE(msg->alpha_rop_flag >> 6))); reg = ((reg & (~m_RGA_ALPHA_CON_AA_SEL)) | (s_RGA_ALPHA_CON_AA_SEL(msg->alpha_rop_flag >> 7))); - + *bRGA_ALPHA_CON = reg; - if(rop_mode == 0) { + if(rop_mode == 0) { rop_con0 = ROP3_code[(msg->rop_code & 0xff)]; } else if(rop_mode == 1) { @@ -804,25 +821,25 @@ RGA_set_alpha_rop(u8 *base, const struct rga_req *msg) rop_con0 = ROP3_code[(msg->rop_code & 0xff)]; rop_con1 = ROP3_code[(msg->rop_code & 0xff00)>>8]; } - + bRGA_ROP_CON0 = (u32 *)(base + RGA_ROP_CON0_OFFSET); bRGA_ROP_CON1 = (u32 *)(base + RGA_ROP_CON1_OFFSET); *bRGA_ROP_CON0 = (u32)rop_con0; - *bRGA_ROP_CON1 = (u32)rop_con1; + *bRGA_ROP_CON1 = (u32)rop_con1; } -/************************************************************* -Func: - RGA_set_color -Description: +/************************************************************* +Func: + RGA_set_color +Description: fill color some relate reg bit bg_color/fg_color -Author: - ZhangShengqin -Date: - 20012-2-2 10:59:25 +Author: + ZhangShengqin +Date: + 20012-2-2 10:59:25 **************************************************************/ void @@ -832,15 +849,15 @@ RGA_set_color(u8 *base, const struct rga_req *msg) u32 *bRGA_SRC_TR_COLOR1; u32 *bRGA_SRC_BG_COLOR; u32 *bRGA_SRC_FG_COLOR; - - + + bRGA_SRC_BG_COLOR = (u32 *)(base + RGA_SRC_BG_COLOR_OFFSET); bRGA_SRC_FG_COLOR = (u32 *)(base + RGA_SRC_FG_COLOR_OFFSET); - + *bRGA_SRC_BG_COLOR = msg->bg_color; /* 1bpp 0 */ *bRGA_SRC_FG_COLOR = msg->fg_color; /* 1bpp 1 */ - - bRGA_SRC_TR_COLOR0 = (u32 *)(base + RGA_SRC_TR_COLOR0_OFFSET); + + bRGA_SRC_TR_COLOR0 = (u32 *)(base + RGA_SRC_TR_COLOR0_OFFSET); bRGA_SRC_TR_COLOR1 = (u32 *)(base + RGA_SRC_TR_COLOR1_OFFSET); *bRGA_SRC_TR_COLOR0 = msg->color_key_min; @@ -848,15 +865,15 @@ RGA_set_color(u8 *base, const struct rga_req *msg) } -/************************************************************* -Func: - RGA_set_fading -Description: +/************************************************************* +Func: + RGA_set_fading +Description: fill fading some relate reg bit -Author: - ZhangShengqin -Date: - 20012-2-2 10:59:25 +Author: + ZhangShengqin +Date: + 20012-2-2 10:59:25 **************************************************************/ s32 @@ -874,21 +891,21 @@ RGA_set_fading(u8 *base, const struct rga_req *msg) reg = (r<<8) | (g<<16) | (b<<24) | reg; - *bRGA_FADING_CON = reg; - + *bRGA_FADING_CON = reg; + return 0; } -/************************************************************* -Func: - RGA_set_pat -Description: +/************************************************************* +Func: + RGA_set_pat +Description: fill patten some relate reg bit -Author: - ZhangShengqin -Date: - 20012-2-2 10:59:25 +Author: + ZhangShengqin +Date: + 20012-2-2 10:59:25 **************************************************************/ s32 @@ -901,7 +918,7 @@ RGA_set_pat(u8 *base, const struct rga_req *msg) bRGA_PAT_START_POINT = (u32 *)(base + RGA_PAT_START_POINT_OFFSET); bRGA_PAT_CON = (u32 *)(base + RGA_PAT_CON_OFFSET); - + *bRGA_PAT_START_POINT = (msg->pat.act_w * msg->pat.y_offset) + msg->pat.x_offset; reg = (msg->pat.act_w - 1) | ((msg->pat.act_h - 1) << 8) | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24); @@ -913,18 +930,18 @@ RGA_set_pat(u8 *base, const struct rga_req *msg) -/************************************************************* -Func: - RGA_set_bitblt_reg_info -Description: +/************************************************************* +Func: + RGA_set_bitblt_reg_info +Description: fill bitblt mode relate ren info -Author: - ZhangShengqin -Date: - 20012-2-2 10:59:25 +Author: + ZhangShengqin +Date: + 20012-2-2 10:59:25 **************************************************************/ -void +void RGA_set_bitblt_reg_info(u8 *base, const struct rga_req * msg, TILE_INFO *tile) { u32 *bRGA_SRC_Y_MST; @@ -960,18 +977,18 @@ RGA_set_bitblt_reg_info(u8 *base, const struct rga_req * msg, TILE_INFO *tile) bRGA_SRC_X_PARA = (u32 *)(base + RGA_SRC_X_PARA_OFFSET); bRGA_SRC_Y_PARA = (u32 *)(base + RGA_SRC_Y_PARA_OFFSET); - + bRGA_SRC_TILE_XINFO = (u32 *)(base + RGA_SRC_TILE_XINFO_OFFSET); bRGA_SRC_TILE_YINFO = (u32 *)(base + RGA_SRC_TILE_YINFO_OFFSET); bRGA_SRC_TILE_H_INCR = (u32 *)(base + RGA_SRC_TILE_H_INCR_OFFSET); - bRGA_SRC_TILE_V_INCR = (u32 *)(base + RGA_SRC_TILE_V_INCR_OFFSET); + bRGA_SRC_TILE_V_INCR = (u32 *)(base + RGA_SRC_TILE_V_INCR_OFFSET); bRGA_SRC_TILE_OFFSETX = (u32 *)(base + RGA_SRC_TILE_OFFSETX_OFFSET); bRGA_SRC_TILE_OFFSETY = (u32 *)(base + RGA_SRC_TILE_OFFSETY_OFFSET); bRGA_DST_MST = (u32 *)(base + RGA_DST_MST_OFFSET); bRGA_DST_CTR_INFO = (u32 *)(base + RGA_DST_CTR_INFO_OFFSET); - /* Matrix reg fill */ + /* Matrix reg fill */ m0 = (s32)(tile->matrix[0] >> 18); m1 = (s32)(tile->matrix[1] >> 18); m2 = (s32)(tile->matrix[2] >> 18); @@ -979,8 +996,8 @@ RGA_set_bitblt_reg_info(u8 *base, const struct rga_req * msg, TILE_INFO *tile) *bRGA_SRC_X_PARA = (m0 & 0xffff) | (m2 << 16); *bRGA_SRC_Y_PARA = (m1 & 0xffff) | (m3 << 16); - - /* src tile information setting */ + + /* src tile information setting */ if(msg->rotate_mode != 0)//add by hxx,2011.7.12,for rtl0707,when line scanning ,do not calc src tile info { *bRGA_SRC_TILE_XINFO = (tile->tile_start_x_coor & 0xffff) | (tile->tile_w << 16); @@ -994,7 +1011,7 @@ RGA_set_bitblt_reg_info(u8 *base, const struct rga_req * msg, TILE_INFO *tile) } pixel_width = RGA_pixel_width_init(msg->src.format); - + stride = ((msg->src.vir_w * pixel_width) + 3) & (~3); if ((msg->rotate_mode == 1)||(msg->rotate_mode == 2)||(msg->rotate_mode == 3)) @@ -1023,11 +1040,11 @@ RGA_set_bitblt_reg_info(u8 *base, const struct rga_req * msg, TILE_INFO *tile) pos[6] >>= 11; pos[7] >>= 11; - xmax = (MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]) + 1); - xmin = (MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6])); + xmax = (MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]) + 1); + xmin = (MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6])); - ymax = (MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]) + 1); - ymin = (MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7])); + ymax = (MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]) + 1); + ymin = (MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7])); xp = xmin + msg->src.x_offset; yp = ymin + msg->src.y_offset; @@ -1037,9 +1054,9 @@ RGA_set_bitblt_reg_info(u8 *base, const struct rga_req * msg, TILE_INFO *tile) xp = CLIP(xp, msg->src.x_offset, msg->src.x_offset + msg->src.act_w - 1); yp = CLIP(yp, msg->src.y_offset, msg->src.y_offset + msg->src.act_h - 1); } - + switch(msg->src.format) - { + { case RK_FORMAT_YCbCr_420_P : y_addr = msg->src.yrgb_addr + yp*stride + xp; u_addr = msg->src.uv_addr + (yp>>1)*(stride>>1) + (xp>>1); @@ -1047,9 +1064,9 @@ RGA_set_bitblt_reg_info(u8 *base, const struct rga_req * msg, TILE_INFO *tile) break; case RK_FORMAT_YCbCr_420_SP : y_addr = msg->src.yrgb_addr + yp*stride + xp; - u_addr = msg->src.uv_addr + (yp>>1)*stride + ((xp>>1)<<1); + u_addr = msg->src.uv_addr + (yp>>1)*stride + ((xp>>1)<<1); break; - case RK_FORMAT_YCbCr_422_P : + case RK_FORMAT_YCbCr_422_P : y_addr = msg->src.yrgb_addr + yp*stride + xp; u_addr = msg->src.uv_addr + (yp)*(stride>>1) + (xp>>1); v_addr = msg->src.v_addr + (yp)*(stride>>1) + (xp>>1); @@ -1065,9 +1082,9 @@ RGA_set_bitblt_reg_info(u8 *base, const struct rga_req * msg, TILE_INFO *tile) break; case RK_FORMAT_YCrCb_420_SP : y_addr = msg->src.yrgb_addr + yp*stride + xp; - u_addr = msg->src.uv_addr + (yp>>1)*stride + ((xp>>1)<<1); + u_addr = msg->src.uv_addr + (yp>>1)*stride + ((xp>>1)<<1); break; - case RK_FORMAT_YCrCb_422_P : + case RK_FORMAT_YCrCb_422_P : y_addr = msg->src.yrgb_addr + yp*stride + xp; u_addr = msg->src.uv_addr + (yp)*(stride>>1) + (xp>>1); v_addr = msg->src.v_addr + (yp)*(stride>>1) + (xp>>1); @@ -1075,7 +1092,7 @@ RGA_set_bitblt_reg_info(u8 *base, const struct rga_req * msg, TILE_INFO *tile) case RK_FORMAT_YCrCb_422_SP: y_addr = msg->src.yrgb_addr + yp*stride + xp; u_addr = msg->src.uv_addr + yp*stride + ((xp>>1)<<1); - break; + break; default : y_addr = msg->src.yrgb_addr + yp*stride + xp*pixel_width; break; @@ -1085,28 +1102,28 @@ RGA_set_bitblt_reg_info(u8 *base, const struct rga_req * msg, TILE_INFO *tile) *bRGA_SRC_CB_MST = u_addr; *bRGA_SRC_CR_MST = v_addr; } - + /*dst info*/ pixel_width = RGA_pixel_width_init(msg->dst.format); stride = (msg->dst.vir_w * pixel_width + 3) & (~3); *bRGA_DST_MST = (u32)msg->dst.yrgb_addr + (tile->dst_ctrl.y_off * stride) + (tile->dst_ctrl.x_off * pixel_width); *bRGA_DST_CTR_INFO = (tile->dst_ctrl.w) | ((tile->dst_ctrl.h) << 16); - *bRGA_DST_CTR_INFO |= (1<<29); + *bRGA_DST_CTR_INFO |= ((1<<29) | (1<<28)); } -/************************************************************* -Func: - RGA_set_color_palette_reg_info -Description: +/************************************************************* +Func: + RGA_set_color_palette_reg_info +Description: fill color palette process some relate reg bit -Author: - ZhangShengqin -Date: - 20012-2-2 10:59:25 +Author: + ZhangShengqin +Date: + 20012-2-2 10:59:25 **************************************************************/ void @@ -1123,27 +1140,27 @@ RGA_set_color_palette_reg_info(u8 *base, const struct rga_req *msg) y_off = msg->src.y_offset; sw = msg->src.vir_w; - shift = 3 - (msg->palette_mode & 3); + shift = 3 - (msg->palette_mode & 3); byte_num = sw >> shift; src_stride = (byte_num + 3) & (~3); - - p = msg->src.yrgb_addr; + + p = msg->src.yrgb_addr; p = p + (x_off>>shift) + y_off*src_stride; - bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET); - *bRGA_SRC_Y_MST = (u32)p; + bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET); + *bRGA_SRC_Y_MST = (u32)p; } -/************************************************************* -Func: - RGA_set_color_fill_reg_info -Description: +/************************************************************* +Func: + RGA_set_color_fill_reg_info +Description: fill color fill process some relate reg bit -Author: - ZhangShengqin -Date: - 20012-2-2 10:59:25 +Author: + ZhangShengqin +Date: + 20012-2-2 10:59:25 **************************************************************/ void RGA_set_color_fill_reg_info(u8 *base, const struct rga_req *msg) @@ -1169,19 +1186,19 @@ RGA_set_color_fill_reg_info(u8 *base, const struct rga_req *msg) *bRGA_CP_GR_R = (msg->gr_color.gr_x_r & 0xffff) | (msg->gr_color.gr_y_r << 16); *bRGA_PAT_CON = (msg->pat.vir_w-1) | ((msg->pat.vir_h-1) << 8) | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24); - + } -/************************************************************* -Func: - RGA_set_line_drawing_reg_info -Description: +/************************************************************* +Func: + RGA_set_line_drawing_reg_info +Description: fill line drawing process some relate reg bit -Author: - ZhangShengqin -Date: - 20012-2-2 10:59:25 +Author: + ZhangShengqin +Date: + 20012-2-2 10:59:25 **************************************************************/ s32 RGA_set_line_drawing_reg_info(u8 *base, const struct rga_req *msg) @@ -1190,9 +1207,9 @@ s32 RGA_set_line_drawing_reg_info(u8 *base, const struct rga_req *msg) u32 *bRGA_DST_VIR_INFO; u32 *bRGA_LINE_DRAW_XY_INFO; u32 *bRGA_LINE_DRAW_WIDTH; - u32 *bRGA_LINE_DRAWING_COLOR; + u32 *bRGA_LINE_DRAWING_COLOR; u32 *bRGA_LINE_DRAWING_MST; - + u32 reg = 0; s16 x_width, y_width; @@ -1202,7 +1219,7 @@ s32 RGA_set_line_drawing_reg_info(u8 *base, const struct rga_req *msg) u32 start_addr; u8 line_dir, dir_major, dir_semi_major; u16 major_width; - + bRGA_LINE_DRAW = (u32 *)(base + RGA_LINE_DRAW_OFFSET); bRGA_DST_VIR_INFO = (u32 *)(base + RGA_DST_VIR_INFO_OFFSET); bRGA_LINE_DRAW_XY_INFO = (u32 *)(base + RGA_LINE_DRAW_XY_INFO_OFFSET); @@ -1214,16 +1231,16 @@ s32 RGA_set_line_drawing_reg_info(u8 *base, const struct rga_req *msg) stride = (msg->dst.vir_w * pw + 3) & (~3); - start_addr = msg->dst.yrgb_addr - + (msg->line_draw_info.start_point.y * stride) + start_addr = msg->dst.yrgb_addr + + (msg->line_draw_info.start_point.y * stride) + (msg->line_draw_info.start_point.x * pw); x_width = msg->line_draw_info.start_point.x - msg->line_draw_info.end_point.x; y_width = msg->line_draw_info.start_point.y - msg->line_draw_info.end_point.y; abs_x = abs(x_width); - abs_y = abs(y_width); - + abs_y = abs(y_width); + if (abs_x >= abs_y) { if (y_width > 0) @@ -1231,20 +1248,20 @@ s32 RGA_set_line_drawing_reg_info(u8 *base, const struct rga_req *msg) else dir_semi_major = 0; - if (x_width > 0) - dir_major = 1; + if (x_width > 0) + dir_major = 1; else dir_major = 0; - if((abs_x == 0)||(abs_y == 0)) - delta = 0; - else + if((abs_x == 0)||(abs_y == 0)) + delta = 0; + else delta = (abs_y<<12)/abs_x; if (delta >> 12) delta -= 1; - - major_width = abs_x; + + major_width = abs_x; line_dir = 0; } else @@ -1258,32 +1275,32 @@ s32 RGA_set_line_drawing_reg_info(u8 *base, const struct rga_req *msg) dir_major = 1; else dir_major = 0; - - delta = (abs_x<<12)/abs_y; + + delta = (abs_x<<12)/abs_y; major_width = abs_y; line_dir = 1; } - + reg = (reg & (~m_RGA_LINE_DRAW_MAJOR_WIDTH)) | (s_RGA_LINE_DRAW_MAJOR_WIDTH(major_width)); reg = (reg & (~m_RGA_LINE_DRAW_LINE_DIRECTION)) | (s_RGA_LINE_DRAW_LINE_DIRECTION(line_dir)); reg = (reg & (~m_RGA_LINE_DRAW_LINE_WIDTH)) | (s_RGA_LINE_DRAW_LINE_WIDTH(msg->line_draw_info.line_width - 1)); - reg = (reg & (~m_RGA_LINE_DRAW_INCR_VALUE)) | (s_RGA_LINE_DRAW_INCR_VALUE(delta)); + reg = (reg & (~m_RGA_LINE_DRAW_INCR_VALUE)) | (s_RGA_LINE_DRAW_INCR_VALUE(delta)); reg = (reg & (~m_RGA_LINE_DRAW_DIR_SEMI_MAJOR)) | (s_RGA_LINE_DRAW_DIR_SEMI_MAJOR(dir_semi_major)); reg = (reg & (~m_RGA_LINE_DRAW_DIR_MAJOR)) | (s_RGA_LINE_DRAW_DIR_MAJOR(dir_major)); reg = (reg & (~m_RGA_LINE_DRAW_LAST_POINT)) | (s_RGA_LINE_DRAW_LAST_POINT(msg->line_draw_info.flag >> 1)); - reg = (reg & (~m_RGA_LINE_DRAW_ANTI_ALISING)) | (s_RGA_LINE_DRAW_ANTI_ALISING(msg->line_draw_info.flag)); + reg = (reg & (~m_RGA_LINE_DRAW_ANTI_ALISING)) | (s_RGA_LINE_DRAW_ANTI_ALISING(msg->line_draw_info.flag)); *bRGA_LINE_DRAW = reg; - + reg = (msg->line_draw_info.start_point.x & 0xfff) | ((msg->line_draw_info.start_point.y & 0xfff) << 16); *bRGA_LINE_DRAW_XY_INFO = reg; - + *bRGA_LINE_DRAW_WIDTH = msg->dst.vir_w; *bRGA_LINE_DRAWING_COLOR = msg->line_draw_info.color; *bRGA_LINE_DRAWING_MST = (u32)start_addr; - + return 0; } @@ -1291,10 +1308,10 @@ s32 RGA_set_line_drawing_reg_info(u8 *base, const struct rga_req *msg) /*full*/ s32 RGA_set_filter_reg_info(u8 *base, const struct rga_req *msg) -{ +{ u32 *bRGA_BLUR_SHARP_INFO; u32 reg = 0; - + bRGA_BLUR_SHARP_INFO = (u32 *)(base + RGA_ALPHA_CON_OFFSET); reg = *bRGA_BLUR_SHARP_INFO; @@ -1303,8 +1320,8 @@ RGA_set_filter_reg_info(u8 *base, const struct rga_req *msg) reg = ((reg & (~m_RGA_BLUR_SHARP_FILTER_MODE)) | (s_RGA_BLUR_SHARP_FILTER_MODE(msg->bsfilter_flag >>2))); *bRGA_BLUR_SHARP_INFO = reg; - - return 0; + + return 0; } @@ -1312,7 +1329,7 @@ RGA_set_filter_reg_info(u8 *base, const struct rga_req *msg) s32 RGA_set_pre_scale_reg_info(u8 *base, const struct rga_req *msg) { - u32 *bRGA_PRE_SCALE_INFO; + u32 *bRGA_PRE_SCALE_INFO; u32 reg = 0; u32 h_ratio = 0; u32 v_ratio = 0; @@ -1329,13 +1346,13 @@ RGA_set_pre_scale_reg_info(u8 *base, const struct rga_req *msg) if((dst_width == 0) || (dst_height == 0)) { printk("pre scale reg info error ratio is divide zero\n"); - return -EINVAL; + return -EINVAL; } h_ratio = (src_width <<16) / dst_width; v_ratio = (src_height<<16) / dst_height; - if (h_ratio <= (1<<16)) + if (h_ratio <= (1<<16)) h_ratio = 0; else if (h_ratio <= (2<<16)) h_ratio = 1; @@ -1344,7 +1361,7 @@ RGA_set_pre_scale_reg_info(u8 *base, const struct rga_req *msg) else if (h_ratio <= (8<<16)) h_ratio = 3; - if (v_ratio <= (1<<16)) + if (v_ratio <= (1<<16)) v_ratio = 0; else if (v_ratio <= (2<<16)) v_ratio = 1; @@ -1354,37 +1371,37 @@ RGA_set_pre_scale_reg_info(u8 *base, const struct rga_req *msg) v_ratio = 3; if(msg->src.format == msg->dst.format) - ps_yuv_flag = 0; - else - ps_yuv_flag = 1; + ps_yuv_flag = 0; + else + ps_yuv_flag = 1; bRGA_PRE_SCALE_INFO = (u32 *)(base + RGA_ALPHA_CON_OFFSET); - + reg = *bRGA_PRE_SCALE_INFO; reg = ((reg & (~m_RGA_PRE_SCALE_HOR_RATIO)) | (s_RGA_PRE_SCALE_HOR_RATIO((u8)h_ratio))); reg = ((reg & (~m_RGA_PRE_SCALE_VER_RATIO)) | (s_RGA_PRE_SCALE_VER_RATIO((u8)v_ratio))); reg = ((reg & (~m_RGA_PRE_SCALE_OUTPUT_FORMAT)) | (s_RGA_PRE_SCALE_OUTPUT_FORMAT(ps_yuv_flag))); *bRGA_PRE_SCALE_INFO = reg; - - return 0; + + return 0; } /*full*/ -int +int RGA_set_update_palette_table_reg_info(u8 *base, const struct rga_req *msg) { u32 *bRGA_LUT_MST; - if (!msg->LUT_addr) { + if (!msg->LUT_addr) { return -1; - } + } bRGA_LUT_MST = (u32 *)(base + RGA_LUT_MST_OFFSET); - - *bRGA_LUT_MST = (u32)msg->LUT_addr; + + *bRGA_LUT_MST = (u32)msg->LUT_addr; return 0; } @@ -1409,7 +1426,7 @@ RGA_set_update_patten_buff_reg_info(u8 *base, const struct rga_req *msg) if ( !pat->yrgb_addr ) { return -1; - } + } *bRGA_PAT_MST = (u32)pat->yrgb_addr; if ((pat->vir_w > 256)||(pat->x_offset > 256)||(pat->y_offset > 256)) { @@ -1418,21 +1435,21 @@ RGA_set_update_patten_buff_reg_info(u8 *base, const struct rga_req *msg) *bRGA_PAT_START_POINT = (pat->vir_w * pat->y_offset) + pat->x_offset; reg = (pat->vir_w-1) | ((pat->vir_h-1) << 8) | (pat->x_offset << 16) | (pat->y_offset << 24); - *bRGA_PAT_CON = reg; - + *bRGA_PAT_CON = reg; + return 0; } -/************************************************************* -Func: - RGA_set_mmu_ctrl_reg_info -Description: - fill mmu relate some reg info -Author: - ZhangShengqin -Date: - 20012-2-2 10:59:25 +/************************************************************* +Func: + RGA_set_mmu_ctrl_reg_info +Description: + fill mmu relate some reg info +Author: + ZhangShengqin +Date: + 20012-2-2 10:59:25 **************************************************************/ s32 @@ -1446,7 +1463,7 @@ RGA_set_mmu_ctrl_reg_info(u8 *base, const struct rga_req *msg) mmu_addr = (u32)msg->mmu_info.base_addr; TLB_size = (msg->mmu_info.mmu_flag >> 4) & 0x3; mmu_enable = msg->mmu_info.mmu_flag & 0x1; - + src_flag = (msg->mmu_info.mmu_flag >> 1) & 0x1; dst_flag = (msg->mmu_info.mmu_flag >> 2) & 0x1; CMD_flag = (msg->mmu_info.mmu_flag >> 3) & 0x1; @@ -1457,7 +1474,7 @@ RGA_set_mmu_ctrl_reg_info(u8 *base, const struct rga_req *msg) reg = ((reg & (~m_RGA_MMU_CTRL_TLB_ADDR)) | s_RGA_MMU_CTRL_TLB_ADDR(mmu_addr)); *RGA_MMU_TLB = reg; - reg = *RGA_MMU_CTRL_ADDR; + reg = *RGA_MMU_CTRL_ADDR; reg = ((reg & (~m_RGA_MMU_CTRL_PAGE_TABLE_SIZE)) | s_RGA_MMU_CTRL_PAGE_TABLE_SIZE(TLB_size)); reg = ((reg & (~m_RGA_MMU_CTRL_MMU_ENABLE)) | s_RGA_MMU_CTRL_MMU_ENABLE(mmu_enable)); reg = ((reg & (~m_RGA_MMU_CTRL_SRC_FLUSH)) | s_RGA_MMU_CTRL_SRC_FLUSH(1)); @@ -1470,47 +1487,47 @@ RGA_set_mmu_ctrl_reg_info(u8 *base, const struct rga_req *msg) -/************************************************************* -Func: - RGA_gen_reg_info -Description: - Generate RGA command reg list from rga_req struct. -Author: - ZhangShengqin -Date: - 20012-2-2 10:59:25 +/************************************************************* +Func: + RGA_gen_reg_info +Description: + Generate RGA command reg list from rga_req struct. +Author: + ZhangShengqin +Date: + 20012-2-2 10:59:25 **************************************************************/ int RGA_gen_reg_info(const struct rga_req *msg, unsigned char *base) { TILE_INFO tile; - memset(base, 0x0, 28*4); + memset(base, 0x0, 28*4); RGA_set_mode_ctrl(base, msg); - + switch(msg->render_mode) { case bitblt_mode : RGA_set_alpha_rop(base, msg); RGA_set_src(base, msg); - RGA_set_dst(base, msg); + RGA_set_dst(base, msg); RGA_set_color(base, msg); RGA_set_fading(base, msg); - RGA_set_pat(base, msg); + RGA_set_pat(base, msg); matrix_cal(msg, &tile); dst_ctrl_cal(msg, &tile); src_tile_info_cal(msg, &tile); - RGA_set_bitblt_reg_info(base, msg, &tile); + RGA_set_bitblt_reg_info(base, msg, &tile); break; case color_palette_mode : RGA_set_src(base, msg); - RGA_set_dst(base, msg); + RGA_set_dst(base, msg); RGA_set_color(base, msg); RGA_set_color_palette_reg_info(base, msg); break; case color_fill_mode : RGA_set_alpha_rop(base, msg); - RGA_set_dst(base, msg); + RGA_set_dst(base, msg); RGA_set_color(base, msg); RGA_set_pat(base, msg); RGA_set_color_fill_reg_info(base, msg); @@ -1528,7 +1545,7 @@ RGA_gen_reg_info(const struct rga_req *msg, unsigned char *base) break; case pre_scaling_mode : RGA_set_src(base, msg); - RGA_set_dst(base, msg); + RGA_set_dst(base, msg); if(RGA_set_pre_scale_reg_info(base, msg) == -EINVAL) return -1; break; @@ -1538,10 +1555,10 @@ RGA_gen_reg_info(const struct rga_req *msg, unsigned char *base) } break; case update_patten_buff_mode: - if (RGA_set_update_patten_buff_reg_info(base, msg)){ + if (RGA_set_update_patten_buff_reg_info(base, msg)){ return -1; } - + break; }