X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fasm-arm%2Fassembler.h;h=911393b2c6f000cc39bf84d73a7385883c105e5f;hb=1503af661947b7a4a09355cc2ae6aa0d43f16776;hp=d53bafa9bf1c58f80fffdb2910571d3544340e1d;hpb=d42510a0f58c2583c37c8e9b7548e3a68545863a;p=firefly-linux-kernel-4.4.55.git

diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index d53bafa9bf1c..911393b2c6f0 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -55,30 +55,21 @@
 #define PLD(code...)
 #endif
 
-#define MODE_USR	USR_MODE
-#define MODE_FIQ	FIQ_MODE
-#define MODE_IRQ	IRQ_MODE
-#define MODE_SVC	SVC_MODE
-
-#define DEFAULT_FIQ	MODE_FIQ
-
 /*
- * LOADREGS - ldm with PC in register list (eg, ldmfd sp!, {pc})
+ * This can be used to enable code to cacheline align the destination
+ * pointer when bulk writing to memory.  Experiments on StrongARM and
+ * XScale didn't show this a worthwhile thing to do when the cache is not
+ * set to write-allocate (this would need further testing on XScale when WA
+ * is used).
+ *
+ * On Feroceon there is much to gain however, regardless of cache mode.
  */
-#ifdef __STDC__
-#define LOADREGS(cond, base, reglist...)\
-	ldm##cond	base,reglist
+#ifdef CONFIG_CPU_FEROCEON
+#define CALGN(code...) code
 #else
-#define LOADREGS(cond, base, reglist...)\
-	ldm/**/cond	base,reglist
+#define CALGN(code...)
 #endif
 
-/*
- * Build a return instruction for this processor type.
- */
-#define RETINSTR(instr, regs...)\
-	instr	regs
-
 /*
  * Enable and disable interrupts
  */
@@ -117,18 +108,6 @@
 	msr	cpsr_c, \oldcpsr
 	.endm
 
-/*
- * These two are used to save LR/restore PC over a user-based access.
- * The old 26-bit architecture requires that we do.  On 32-bit
- * architecture, we can safely ignore this requirement.
- */
-	.macro	save_lr
-	.endm
-
-	.macro	restore_pc
-	mov	pc, lr
-	.endm
-
 #define USER(x...)				\
 9999:	x;					\
 	.section __ex_table,"a";		\