X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FCodeGen%2FCallingConvLower.h;h=9df41dd0257c5f85cc329fd33127b8d1fe209075;hb=c7fdae24002e6bc92c0acdd16a0298345d87866f;hp=0fa297a6639194abc1b4c9ce3015c9433b3f7059;hpb=471e4224809f51652c71f319532697a879a75a0d;p=oota-llvm.git diff --git a/include/llvm/CodeGen/CallingConvLower.h b/include/llvm/CodeGen/CallingConvLower.h index 0fa297a6639..9df41dd0257 100644 --- a/include/llvm/CodeGen/CallingConvLower.h +++ b/include/llvm/CodeGen/CallingConvLower.h @@ -16,31 +16,41 @@ #define LLVM_CODEGEN_CALLINGCONVLOWER_H #include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/ValueTypes.h" +#include "llvm/IR/CallingConv.h" +#include "llvm/MC/MCRegisterInfo.h" #include "llvm/Target/TargetCallingConv.h" -#include "llvm/CallingConv.h" namespace llvm { - class TargetRegisterInfo; - class TargetMachine; - class CCState; +class CCState; +class MVT; +class TargetMachine; +class TargetRegisterInfo; /// CCValAssign - Represent assignment of one arg/retval to a location. class CCValAssign { public: enum LocInfo { - Full, // The value fills the full location. - SExt, // The value is sign extended in the location. - ZExt, // The value is zero extended in the location. - AExt, // The value is extended with undefined upper bits. - BCvt, // The value is bit-converted in the location. - VExt, // The value is vector-widened in the location. - // FIXME: Not implemented yet. Code that uses AExt to mean - // vector-widen should be fixed to use VExt instead. - Indirect // The location contains pointer to the value. + Full, // The value fills the full location. + SExt, // The value is sign extended in the location. + ZExt, // The value is zero extended in the location. + AExt, // The value is extended with undefined upper bits. + SExtUpper, // The value is in the upper bits of the location and should be + // sign extended when retrieved. + ZExtUpper, // The value is in the upper bits of the location and should be + // zero extended when retrieved. + AExtUpper, // The value is in the upper bits of the location and should be + // extended with undefined upper bits when retrieved. + BCvt, // The value is bit-converted in the location. + VExt, // The value is vector-widened in the location. + // FIXME: Not implemented yet. Code that uses AExt to mean + // vector-widen should be fixed to use VExt instead. + FPExt, // The floating-point value is fp-extended in the location. + Indirect // The location contains pointer to the value. // TODO: a subset of the value is in the location. }; + private: /// ValNo - This is the value number begin assigned (e.g. an argument number). unsigned ValNo; @@ -49,10 +59,10 @@ private: unsigned Loc; /// isMem - True if this is a memory loc, false if it is a register loc. - bool isMem : 1; + unsigned isMem : 1; /// isCustom - True if this arg/retval requires special handling. - bool isCustom : 1; + unsigned isCustom : 1; /// Information about how the value is assigned. LocInfo HTP : 6; @@ -110,6 +120,23 @@ public: return Ret; } + // There is no need to differentiate between a pending CCValAssign and other + // kinds, as they are stored in a different list. + static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT, + LocInfo HTP, unsigned ExtraInfo = 0) { + return getReg(ValNo, ValVT, ExtraInfo, LocVT, HTP); + } + + void convertToReg(unsigned RegNo) { + Loc = RegNo; + isMem = false; + } + + void convertToMem(unsigned Offset) { + Loc = Offset; + isMem = true; + } + unsigned getValNo() const { return ValNo; } MVT getValVT() const { return ValVT; } @@ -120,6 +147,7 @@ public: unsigned getLocReg() const { assert(isRegLoc()); return Loc; } unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; } + unsigned getExtraInfo() const { return Loc; } MVT getLocVT() const { return LocVT; } LocInfo getLocInfo() const { return HTP; } @@ -127,6 +155,19 @@ public: return (HTP == AExt || HTP == SExt || HTP == ZExt); } + bool isUpperBitsInLoc() const { + return HTP == AExtUpper || HTP == SExtUpper || HTP == ZExtUpper; + } +}; + +/// Describes a register that needs to be forwarded from the prologue to a +/// musttail call. +struct ForwardedRegister { + ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT) + : VReg(VReg), PReg(PReg), VT(VT) {} + unsigned VReg; + MCPhysReg PReg; + MVT VT; }; /// CCAssignFn - This function assigns a location for Val, updating State to @@ -142,41 +183,106 @@ typedef bool CCCustomFn(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State); -typedef enum { Invalid, Prologue, Call } ParmContext; +/// ParmContext - This enum tracks whether calling convention lowering is in +/// the context of prologue or call generation. Not all backends make use of +/// this information. +typedef enum { Unknown, Prologue, Call } ParmContext; /// CCState - This class holds information needed while lowering arguments and /// return values. It captures which registers are already assigned and which /// stack slots are used. It provides accessors to allocate these values. class CCState { +private: CallingConv::ID CallingConv; bool IsVarArg; MachineFunction &MF; - const TargetMachine &TM; const TargetRegisterInfo &TRI; - SmallVector &Locs; + SmallVectorImpl &Locs; LLVMContext &Context; unsigned StackOffset; + unsigned MaxStackArgAlign; SmallVector UsedRegs; - unsigned FirstByValReg; - bool FirstByValRegValid; + SmallVector PendingLocs; + + // ByValInfo and SmallVector ByValRegs: + // + // Vector of ByValInfo instances (ByValRegs) is introduced for byval registers + // tracking. + // Or, in another words it tracks byval parameters that are stored in + // general purpose registers. + // + // For 4 byte stack alignment, + // instance index means byval parameter number in formal + // arguments set. Assume, we have some "struct_type" with size = 4 bytes, + // then, for function "foo": + // + // i32 foo(i32 %p, %struct_type* %r, i32 %s, %struct_type* %t) + // + // ByValRegs[0] describes how "%r" is stored (Begin == r1, End == r2) + // ByValRegs[1] describes how "%t" is stored (Begin == r3, End == r4). + // + // In case of 8 bytes stack alignment, + // ByValRegs may also contain information about wasted registers. + // In function shown above, r3 would be wasted according to AAPCS rules. + // And in that case ByValRegs[1].Waste would be "true". + // ByValRegs vector size still would be 2, + // while "%t" goes to the stack: it wouldn't be described in ByValRegs. + // + // Supposed use-case for this collection: + // 1. Initially ByValRegs is empty, InRegsParamsProcessed is 0. + // 2. HandleByVal fillups ByValRegs. + // 3. Argument analysis (LowerFormatArguments, for example). After + // some byval argument was analyzed, InRegsParamsProcessed is increased. + struct ByValInfo { + ByValInfo(unsigned B, unsigned E, bool IsWaste = false) : + Begin(B), End(E), Waste(IsWaste) {} + // First register allocated for current parameter. + unsigned Begin; + + // First after last register allocated for current parameter. + unsigned End; + + // Means that current range of registers doesn't belong to any + // parameters. It was wasted due to stack alignment rules. + // For more information see: + // AAPCS, 5.5 Parameter Passing, Stage C, C.3. + bool Waste; + }; + SmallVector ByValRegs; + + // InRegsParamsProcessed - shows how many instances of ByValRegs was proceed + // during argument analysis. + unsigned InRegsParamsProcessed; + +protected: ParmContext CallOrPrologue; + public: CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, - const TargetMachine &TM, - SmallVector &locs, LLVMContext &C); + SmallVectorImpl &locs, LLVMContext &C); void addLoc(const CCValAssign &V) { Locs.push_back(V); } LLVMContext &getContext() const { return Context; } - const TargetMachine &getTarget() const { return TM; } MachineFunction &getMachineFunction() const { return MF; } CallingConv::ID getCallingConv() const { return CallingConv; } bool isVarArg() const { return IsVarArg; } - unsigned getNextStackOffset() const { return StackOffset; } + /// getNextStackOffset - Return the next stack offset such that all stack + /// slots satisfy their alignment requirements. + unsigned getNextStackOffset() const { + return StackOffset; + } + + /// getAlignedCallFrameSize - Return the size of the call frame needed to + /// be able to store all arguments and such that the alignment requirement + /// of each of the arguments is satisfied. + unsigned getAlignedCallFrameSize() const { + return RoundUpToAlignment(StackOffset, MaxStackArgAlign); + } /// isAllocated - Return true if the specified register (or an alias) is /// allocated. @@ -220,13 +326,13 @@ public: /// produce a single value. void AnalyzeCallResult(MVT VT, CCAssignFn Fn); - /// getFirstUnallocated - Return the first unallocated register in the set, or - /// NumRegs if they are all allocated. - unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { - for (unsigned i = 0; i != NumRegs; ++i) + /// getFirstUnallocated - Return the index of the first unallocated register + /// in the set, or Regs.size() if they are all allocated. + unsigned getFirstUnallocated(ArrayRef Regs) const { + for (unsigned i = 0; i < Regs.size(); ++i) if (!isAllocated(Regs[i])) return i; - return NumRegs; + return Regs.size(); } /// AllocateReg - Attempt to allocate one register. If it is not available, @@ -249,9 +355,9 @@ public: /// AllocateReg - Attempt to allocate one of the specified registers. If none /// are available, return zero. Otherwise, return the first one available, /// marking it and any aliases as allocated. - unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { - unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); - if (FirstUnalloc == NumRegs) + unsigned AllocateReg(ArrayRef Regs) { + unsigned FirstUnalloc = getFirstUnallocated(Regs); + if (FirstUnalloc == Regs.size()) return 0; // Didn't find the reg. // Mark the register and any aliases as allocated. @@ -260,11 +366,39 @@ public: return Reg; } + /// AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive + /// registers. If this is not possible, return zero. Otherwise, return the first + /// register of the block that were allocated, marking the entire block as allocated. + unsigned AllocateRegBlock(ArrayRef Regs, unsigned RegsRequired) { + if (RegsRequired > Regs.size()) + return 0; + + for (unsigned StartIdx = 0; StartIdx <= Regs.size() - RegsRequired; + ++StartIdx) { + bool BlockAvailable = true; + // Check for already-allocated regs in this block + for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) { + if (isAllocated(Regs[StartIdx + BlockIdx])) { + BlockAvailable = false; + break; + } + } + if (BlockAvailable) { + // Mark the entire block as allocated + for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) { + MarkAllocated(Regs[StartIdx + BlockIdx]); + } + return Regs[StartIdx]; + } + } + // No block was available + return 0; + } + /// Version of AllocateReg with list of registers to be shadowed. - unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, - unsigned NumRegs) { - unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); - if (FirstUnalloc == NumRegs) + unsigned AllocateReg(ArrayRef Regs, const MCPhysReg *ShadowRegs) { + unsigned FirstUnalloc = getFirstUnallocated(Regs); + if (FirstUnalloc == Regs.size()) return 0; // Didn't find the reg. // Mark the register and any aliases as allocated. @@ -277,10 +411,12 @@ public: /// AllocateStack - Allocate a chunk of stack space with the specified size /// and alignment. unsigned AllocateStack(unsigned Size, unsigned Align) { - assert(Align && ((Align-1) & Align) == 0); // Align is power of 2. - StackOffset = ((StackOffset + Align-1) & ~(Align-1)); + assert(Align && ((Align - 1) & Align) == 0); // Align is power of 2. + StackOffset = RoundUpToAlignment(StackOffset, Align); unsigned Result = StackOffset; StackOffset += Size; + MaxStackArgAlign = std::max(Align, MaxStackArgAlign); + MF.getFrameInfo()->ensureMaxAlignment(Align); return Result; } @@ -290,6 +426,15 @@ public: return AllocateStack(Size, Align); } + /// Version of AllocateStack with list of extra registers to be shadowed. + /// Note that, unlike AllocateReg, this shadows ALL of the shadow registers. + unsigned AllocateStack(unsigned Size, unsigned Align, + ArrayRef ShadowRegs) { + for (unsigned i = 0; i < ShadowRegs.size(); ++i) + MarkAllocated(ShadowRegs[i]); + return AllocateStack(Size, Align); + } + // HandleByVal - Allocate a stack slot large enough to pass an argument by // value. The size and alignment information of the argument is encoded in its // parameter attribute. @@ -297,15 +442,70 @@ public: MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags); - // First GPR that carries part of a byval aggregate that's split - // between registers and memory. - unsigned getFirstByValReg() { return FirstByValRegValid ? FirstByValReg : 0; } - void setFirstByValReg(unsigned r) { FirstByValReg = r; FirstByValRegValid = true; } - void clearFirstByValReg() { FirstByValReg = 0; FirstByValRegValid = false; } - bool isFirstByValRegValid() { return FirstByValRegValid; } + // Returns count of byval arguments that are to be stored (even partly) + // in registers. + unsigned getInRegsParamsCount() const { return ByValRegs.size(); } + + // Returns count of byval in-regs arguments proceed. + unsigned getInRegsParamsProcessed() const { return InRegsParamsProcessed; } + + // Get information about N-th byval parameter that is stored in registers. + // Here "ByValParamIndex" is N. + void getInRegsParamInfo(unsigned InRegsParamRecordIndex, + unsigned& BeginReg, unsigned& EndReg) const { + assert(InRegsParamRecordIndex < ByValRegs.size() && + "Wrong ByVal parameter index"); + + const ByValInfo& info = ByValRegs[InRegsParamRecordIndex]; + BeginReg = info.Begin; + EndReg = info.End; + } + + // Add information about parameter that is kept in registers. + void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd) { + ByValRegs.push_back(ByValInfo(RegBegin, RegEnd)); + } + + // Goes either to next byval parameter (excluding "waste" record), or + // to the end of collection. + // Returns false, if end is reached. + bool nextInRegsParam() { + unsigned e = ByValRegs.size(); + if (InRegsParamsProcessed < e) + ++InRegsParamsProcessed; + return InRegsParamsProcessed < e; + } + + // Clear byval registers tracking info. + void clearByValRegsInfo() { + InRegsParamsProcessed = 0; + ByValRegs.clear(); + } + + // Rewind byval registers tracking info. + void rewindByValRegsInfo() { + InRegsParamsProcessed = 0; + } + + ParmContext getCallOrPrologue() const { return CallOrPrologue; } + + // Get list of pending assignments + SmallVectorImpl &getPendingLocs() { + return PendingLocs; + } - ParmContext getCallOrPrologue() { return CallOrPrologue; } - void setCallOrPrologue(ParmContext pc) { CallOrPrologue = pc; } + /// Compute the remaining unused register parameters that would be used for + /// the given value type. This is useful when varargs are passed in the + /// registers that normal prototyped parameters would be passed in, or for + /// implementing perfect forwarding. + void getRemainingRegParmsForType(SmallVectorImpl &Regs, MVT VT, + CCAssignFn Fn); + + /// Compute the set of registers that need to be preserved and forwarded to + /// any musttail calls. + void analyzeMustTailForwardedRegisters( + SmallVectorImpl &Forwards, ArrayRef RegParmTypes, + CCAssignFn Fn); private: /// MarkAllocated - Mark a register and all of its aliases as allocated.