X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FCodeGen%2FFastISel.h;h=113dcc7c78ad661bf1f392b8e6ca0169c85424a5;hb=3c7b3fecacee40df7b9a99d290638398b5a62173;hp=b1f73cba30cb2f300d6ece90abccd82ba7858edc;hpb=11609451a5e9921d02dea5f1b6c6cd362a3cd676;p=oota-llvm.git diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h index b1f73cba30c..113dcc7c78a 100644 --- a/include/llvm/CodeGen/FastISel.h +++ b/include/llvm/CodeGen/FastISel.h @@ -18,6 +18,7 @@ #ifndef NDEBUG #include "llvm/ADT/SmallSet.h" #endif +#include "llvm/CodeGen/ValueTypes.h" namespace llvm { @@ -27,6 +28,7 @@ class Instruction; class MachineBasicBlock; class MachineConstantPool; class MachineFunction; +class MachineInstr; class MachineFrameInfo; class MachineRegisterInfo; class TargetData; @@ -34,6 +36,7 @@ class TargetInstrInfo; class TargetLowering; class TargetMachine; class TargetRegisterClass; +class TargetRegisterInfo; /// FastISel - This is a fast-path instruction selection class that /// generates poor code and doesn't support illegal types or non-trivial @@ -45,8 +48,9 @@ protected: DenseMap &ValueMap; DenseMap &MBBMap; DenseMap &StaticAllocaMap; + std::vector > &PHINodesToUpdate; #ifndef NDEBUG - SmallSet &CatchInfoLost; + SmallSet &CatchInfoLost; #endif MachineFunction &MF; MachineRegisterInfo &MRI; @@ -57,6 +61,8 @@ protected: const TargetData &TD; const TargetInstrInfo &TII; const TargetLowering &TLI; + const TargetRegisterInfo &TRI; + bool IsBottomUp; public: /// startNewBlock - Set the current block to which generated machine @@ -74,11 +80,6 @@ public: MBB = mbb; } - /// setCurDebugLoc - Set the current debug location information, which is used - /// when creating a machine instruction. - /// - void setCurDebugLoc(DebugLoc dl) { DL = dl; } - /// getCurDebugLoc() - Return current debug location information. DebugLoc getCurDebugLoc() const { return DL; } @@ -86,28 +87,28 @@ public: /// LLVM IR instruction, and append generated machine instructions to /// the current block. Return true if selection was successful. /// - bool SelectInstruction(Instruction *I); + bool SelectInstruction(const Instruction *I); /// SelectOperator - Do "fast" instruction selection for the given /// LLVM IR operator (Instruction or ConstantExpr), and append /// generated machine instructions to the current block. Return true /// if selection was successful. /// - bool SelectOperator(User *I, unsigned Opcode); + bool SelectOperator(const User *I, unsigned Opcode); /// getRegForValue - Create a virtual register and arrange for it to /// be assigned the value for the given LLVM value. - unsigned getRegForValue(Value *V); + unsigned getRegForValue(const Value *V); /// lookUpRegForValue - Look up the value to see if its value is already /// cached in a register. It may be defined by instructions across blocks or /// defined locally. - unsigned lookUpRegForValue(Value *V); + unsigned lookUpRegForValue(const Value *V); /// getRegForGEPIndex - This is a wrapper around getRegForValue that also /// takes care of truncating or sign-extending the given getelementptr /// index value. - unsigned getRegForGEPIndex(Value *V); + std::pair getRegForGEPIndex(const Value *V); virtual ~FastISel(); @@ -115,9 +116,10 @@ protected: FastISel(MachineFunction &mf, DenseMap &vm, DenseMap &bm, - DenseMap &am + DenseMap &am, + std::vector > &PHINodesToUpdate #ifndef NDEBUG - , SmallSet &cil + , SmallSet &cil #endif ); @@ -127,7 +129,7 @@ protected: /// fit into FastISel's framework. It returns true if it was successful. /// virtual bool - TargetSelectInstruction(Instruction *I) = 0; + TargetSelectInstruction(const Instruction *I) = 0; /// FastEmit_r - This method is called by target-independent code /// to request that an instruction with the given type and opcode @@ -142,7 +144,8 @@ protected: /// virtual unsigned FastEmit_r(MVT VT, MVT RetVT, - unsigned Opcode, unsigned Op0); + unsigned Opcode, + unsigned Op0, bool Op0IsKill); /// FastEmit_rr - This method is called by target-independent code /// to request that an instruction with the given type, opcode, and @@ -151,7 +154,8 @@ protected: virtual unsigned FastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, - unsigned Op0, unsigned Op1); + unsigned Op0, bool Op0IsKill, + unsigned Op1, bool Op1IsKill); /// FastEmit_ri - This method is called by target-independent code /// to request that an instruction with the given type, opcode, and @@ -160,7 +164,8 @@ protected: virtual unsigned FastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, - unsigned Op0, uint64_t Imm); + unsigned Op0, bool Op0IsKill, + uint64_t Imm); /// FastEmit_rf - This method is called by target-independent code /// to request that an instruction with the given type, opcode, and @@ -169,7 +174,8 @@ protected: virtual unsigned FastEmit_rf(MVT VT, MVT RetVT, unsigned Opcode, - unsigned Op0, ConstantFP *FPImm); + unsigned Op0, bool Op0IsKill, + const ConstantFP *FPImm); /// FastEmit_rri - This method is called by target-independent code /// to request that an instruction with the given type, opcode, and @@ -178,7 +184,9 @@ protected: virtual unsigned FastEmit_rri(MVT VT, MVT RetVT, unsigned Opcode, - unsigned Op0, unsigned Op1, uint64_t Imm); + unsigned Op0, bool Op0IsKill, + unsigned Op1, bool Op1IsKill, + uint64_t Imm); /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries /// to emit an instruction with an immediate operand using FastEmit_ri. @@ -186,8 +194,8 @@ protected: /// FastEmit_rr instead. unsigned FastEmit_ri_(MVT VT, unsigned Opcode, - unsigned Op0, uint64_t Imm, - MVT ImmType); + unsigned Op0, bool Op0IsKill, + uint64_t Imm, MVT ImmType); /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries /// to emit an instruction with an immediate operand using FastEmit_rf. @@ -195,8 +203,8 @@ protected: /// FastEmit_rr instead. unsigned FastEmit_rf_(MVT VT, unsigned Opcode, - unsigned Op0, ConstantFP *FPImm, - MVT ImmType); + unsigned Op0, bool Op0IsKill, + const ConstantFP *FPImm, MVT ImmType); /// FastEmit_i - This method is called by target-independent code /// to request that an instruction with the given type, opcode, and @@ -212,7 +220,7 @@ protected: virtual unsigned FastEmit_f(MVT VT, MVT RetVT, unsigned Opcode, - ConstantFP *FPImm); + const ConstantFP *FPImm); /// FastEmitInst_ - Emit a MachineInstr with no operands and a /// result register in the given register class. @@ -225,35 +233,40 @@ protected: /// unsigned FastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0); + unsigned Op0, bool Op0IsKill); /// FastEmitInst_rr - Emit a MachineInstr with two register operands /// and a result register in the given register class. /// unsigned FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0, unsigned Op1); + unsigned Op0, bool Op0IsKill, + unsigned Op1, bool Op1IsKill); /// FastEmitInst_ri - Emit a MachineInstr with two register operands /// and a result register in the given register class. /// unsigned FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0, uint64_t Imm); + unsigned Op0, bool Op0IsKill, + uint64_t Imm); /// FastEmitInst_rf - Emit a MachineInstr with two register operands /// and a result register in the given register class. /// unsigned FastEmitInst_rf(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0, ConstantFP *FPImm); + unsigned Op0, bool Op0IsKill, + const ConstantFP *FPImm); /// FastEmitInst_rri - Emit a MachineInstr with two register operands, /// an immediate, and a result register in the given register class. /// unsigned FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0, unsigned Op1, uint64_t Imm); + unsigned Op0, bool Op0IsKill, + unsigned Op1, bool Op1IsKill, + uint64_t Imm); /// FastEmitInst_i - Emit a MachineInstr with a single immediate /// operand, and a result register in the given register class. @@ -264,46 +277,63 @@ protected: /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg /// from a specified index of a superregister to a specified type. unsigned FastEmitInst_extractsubreg(MVT RetVT, - unsigned Op0, uint32_t Idx); + unsigned Op0, bool Op0IsKill, + uint32_t Idx); /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op /// with all but the least significant bit set to zero. unsigned FastEmitZExtFromI1(MVT VT, - unsigned Op); + unsigned Op0, bool Op0IsKill); /// FastEmitBranch - Emit an unconditional branch to the given block, /// unless it is the immediate (fall-through) successor, and update /// the CFG. - void FastEmitBranch(MachineBasicBlock *MBB); + void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL); - unsigned UpdateValueMap(Value* I, unsigned Reg); + unsigned UpdateValueMap(const Value* I, unsigned Reg); unsigned createResultReg(const TargetRegisterClass *RC); /// TargetMaterializeConstant - Emit a constant in a register using /// target-specific logic, such as constant pool loads. - virtual unsigned TargetMaterializeConstant(Constant* C) { + virtual unsigned TargetMaterializeConstant(const Constant* C) { return 0; } /// TargetMaterializeAlloca - Emit an alloca address in a register using /// target-specific logic. - virtual unsigned TargetMaterializeAlloca(AllocaInst* C) { + virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) { return 0; } private: - bool SelectBinaryOp(User *I, unsigned ISDOpcode); + bool SelectBinaryOp(const User *I, unsigned ISDOpcode); - bool SelectFNeg(User *I); + bool SelectFNeg(const User *I); - bool SelectGetElementPtr(User *I); + bool SelectGetElementPtr(const User *I); - bool SelectCall(User *I); + bool SelectCall(const User *I); - bool SelectBitCast(User *I); + bool SelectBitCast(const User *I); - bool SelectCast(User *I, unsigned Opcode); + bool SelectCast(const User *I, unsigned Opcode); + + /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks. + /// Emit code to ensure constants are copied into registers when needed. + /// Remember the virtual registers that need to be added to the Machine PHI + /// nodes as input. We cannot just directly add them, because expansion + /// might result in multiple MBB's for one BB. As such, the start of the + /// BB might correspond to a different MBB than the end. + bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB); + + /// materializeRegForValue - Helper for getRegForVale. This function is + /// called when the value isn't already available in a register and must + /// be materialized with new instructions. + unsigned materializeRegForValue(const Value *V, MVT VT); + + /// hasTrivialKill - Test whether the given value has exactly one use. + bool hasTrivialKill(const Value *V) const; }; }