X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FCodeGen%2FFastISel.h;h=c7ec6a024b84859ce07d044ff6e86e50d0962c4b;hb=255907042245b77779e3e38c5ce66901866cabe5;hp=c35d43dc287f54cefcc1ce78fe8690f27b335f0c;hpb=d68a07650cdb2e18f18f362ba533459aa10e01b6;p=oota-llvm.git diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h index c35d43dc287..c7ec6a024b8 100644 --- a/include/llvm/CodeGen/FastISel.h +++ b/include/llvm/CodeGen/FastISel.h @@ -1,4 +1,4 @@ -//===-- FastISel.h - Definition of the FastISel class ---------------------===// +//===-- FastISel.h - Definition of the FastISel class ---*- C++ -*---------===// // // The LLVM Compiler Infrastructure // @@ -6,290 +6,418 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -// -// This file defines the FastISel class. -// +/// +/// \file +/// This file defines the FastISel class. +/// //===----------------------------------------------------------------------===// - + #ifndef LLVM_CODEGEN_FASTISEL_H #define LLVM_CODEGEN_FASTISEL_H #include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/SmallSet.h" -#include "llvm/CodeGen/SelectionDAGNodes.h" +#include "llvm/CodeGen/MachineBasicBlock.h" namespace llvm { class AllocaInst; +class Constant; class ConstantFP; +class CallInst; +class DataLayout; +class FunctionLoweringInfo; class Instruction; -class MachineBasicBlock; +class LoadInst; +class MVT; class MachineConstantPool; -class MachineFunction; class MachineFrameInfo; -class MachineModuleInfo; +class MachineFunction; +class MachineInstr; class MachineRegisterInfo; -class TargetData; class TargetInstrInfo; +class TargetLibraryInfo; class TargetLowering; class TargetMachine; class TargetRegisterClass; +class TargetRegisterInfo; +class User; +class Value; -/// FastISel - This is a fast-path instruction selection class that -/// generates poor code and doesn't support illegal types or non-trivial -/// lowering, but runs quickly. +/// This is a fast-path instruction selection class that generates poor code and +/// doesn't support illegal types or non-trivial lowering, but runs quickly. class FastISel { protected: - MachineBasicBlock *MBB; DenseMap LocalValueMap; - DenseMap &ValueMap; - DenseMap &MBBMap; - DenseMap &StaticAllocaMap; -#ifndef NDEBUG - SmallSet &CatchInfoLost; -#endif - MachineFunction &MF; - MachineModuleInfo *MMI; + FunctionLoweringInfo &FuncInfo; MachineRegisterInfo &MRI; MachineFrameInfo &MFI; MachineConstantPool &MCP; + DebugLoc DbgLoc; const TargetMachine &TM; - const TargetData &TD; + const DataLayout &DL; const TargetInstrInfo &TII; const TargetLowering &TLI; + const TargetRegisterInfo &TRI; + const TargetLibraryInfo *LibInfo; + + /// The position of the last instruction for materializing constants for use + /// in the current block. It resets to EmitStartPt when it makes sense (for + /// example, it's usually profitable to avoid function calls between the + /// definition and the use) + MachineInstr *LastLocalValue; + + /// The top most instruction in the current block that is allowed for emitting + /// local variables. LastLocalValue resets to EmitStartPt when it makes sense + /// (for example, on function calls) + MachineInstr *EmitStartPt; public: - /// startNewBlock - Set the current block, to which generated - /// machine instructions will be appended, and clear the local - /// CSE map. - /// - void startNewBlock(MachineBasicBlock *mbb) { - setCurrentBlock(mbb); - LocalValueMap.clear(); + /// Return the position of the last instruction emitted for materializing + /// constants for use in the current block. + MachineInstr *getLastLocalValue() { return LastLocalValue; } + + /// Update the position of the last instruction emitted for materializing + /// constants for use in the current block. + void setLastLocalValue(MachineInstr *I) { + EmitStartPt = I; + LastLocalValue = I; } - /// setCurrentBlock - Set the current block, to which generated - /// machine instructions will be appended. - /// - void setCurrentBlock(MachineBasicBlock *mbb) { - MBB = mbb; - } + /// Set the current block to which generated machine instructions will be + /// appended, and clear the local CSE map. + void startNewBlock(); - /// SelectInstruction - Do "fast" instruction selection for the given - /// LLVM IR instruction, and append generated machine instructions to - /// the current block. Return true if selection was successful. + /// Return current debug location information. + DebugLoc getCurDebugLoc() const { return DbgLoc; } + + /// Do "fast" instruction selection for function arguments and append machine + /// instructions to the current block. Return true if it is successful. + bool LowerArguments(); + + /// Do "fast" instruction selection for the given LLVM IR instruction, and + /// append generated machine instructions to the current block. Return true if + /// selection was successful. + bool SelectInstruction(const Instruction *I); + + /// Do "fast" instruction selection for the given LLVM IR operator + /// (Instruction or ConstantExpr), and append generated machine instructions + /// to the current block. Return true if selection was successful. + bool SelectOperator(const User *I, unsigned Opcode); + + /// Create a virtual register and arrange for it to be assigned the value for + /// the given LLVM value. + unsigned getRegForValue(const Value *V); + + /// Look up the value to see if its value is already cached in a register. It + /// may be defined by instructions across blocks or defined locally. + unsigned lookUpRegForValue(const Value *V); + + /// This is a wrapper around getRegForValue that also takes care of truncating + /// or sign-extending the given getelementptr index value. + std::pair getRegForGEPIndex(const Value *V); + + /// \brief We're checking to see if we can fold \p LI into \p FoldInst. Note + /// that we could have a sequence where multiple LLVM IR instructions are + /// folded into the same machineinstr. For example we could have: /// - bool SelectInstruction(Instruction *I); - - /// SelectInstruction - Do "fast" instruction selection for the given - /// LLVM IR operator (Instruction or ConstantExpr), and append - /// generated machine instructions to the current block. Return true - /// if selection was successful. + /// A: x = load i32 *P + /// B: y = icmp A, 42 + /// C: br y, ... + /// + /// In this scenario, \p LI is "A", and \p FoldInst is "C". We know about "B" + /// (and any other folded instructions) because it is between A and C. /// - bool SelectOperator(User *I, unsigned Opcode); + /// If we succeed folding, return true. + bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst); - /// TargetSelectInstruction - This method is called by target-independent - /// code when the normal FastISel process fails to select an instruction. - /// This gives targets a chance to emit code for anything that doesn't - /// fit into FastISel's framework. It returns true if it was successful. + /// \brief The specified machine instr operand is a vreg, and that vreg is + /// being provided by the specified load instruction. If possible, try to + /// fold the load as an operand to the instruction, returning true if + /// possible. /// - virtual bool - TargetSelectInstruction(Instruction *I) = 0; + /// This method should be implemented by targets. + virtual bool tryToFoldLoadIntoMI(MachineInstr * /*MI*/, unsigned /*OpNo*/, + const LoadInst * /*LI*/) { + return false; + } - /// getRegForValue - Create a virtual register and arrange for it to - /// be assigned the value for the given LLVM value. - unsigned getRegForValue(Value *V); + /// Reset InsertPt to prepare for inserting instructions into the current + /// block. + void recomputeInsertPt(); - /// lookUpRegForValue - Look up the value to see if its value is already - /// cached in a register. It may be defined by instructions across blocks or - /// defined locally. - unsigned lookUpRegForValue(Value *V); + /// Remove all dead instructions between the I and E. + void removeDeadCode(MachineBasicBlock::iterator I, + MachineBasicBlock::iterator E); - /// getRegForGEPIndex - This is a wrapper around getRegForValue that also - /// takes care of truncating or sign-extending the given getelementptr - /// index value. - unsigned getRegForGEPIndex(Value *V); + struct SavePoint { + MachineBasicBlock::iterator InsertPt; + DebugLoc DL; + }; + + /// Prepare InsertPt to begin inserting instructions into the local value area + /// and return the old insert position. + SavePoint enterLocalValueArea(); + + /// Reset InsertPt to the given old insert position. + void leaveLocalValueArea(SavePoint Old); virtual ~FastISel(); protected: - FastISel(MachineFunction &mf, - MachineModuleInfo *mmi, - DenseMap &vm, - DenseMap &bm, - DenseMap &am -#ifndef NDEBUG - , SmallSet &cil -#endif - ); - - /// FastEmit_r - This method is called by target-independent code - /// to request that an instruction with the given type and opcode - /// be emitted. - virtual unsigned FastEmit_(MVT::SimpleValueType VT, - MVT::SimpleValueType RetVT, - ISD::NodeType Opcode); - - /// FastEmit_r - This method is called by target-independent code - /// to request that an instruction with the given type, opcode, and - /// register operand be emitted. - /// - virtual unsigned FastEmit_r(MVT::SimpleValueType VT, - MVT::SimpleValueType RetVT, - ISD::NodeType Opcode, unsigned Op0); + explicit FastISel(FunctionLoweringInfo &funcInfo, + const TargetLibraryInfo *libInfo); - /// FastEmit_rr - This method is called by target-independent code - /// to request that an instruction with the given type, opcode, and - /// register operands be emitted. - /// - virtual unsigned FastEmit_rr(MVT::SimpleValueType VT, - MVT::SimpleValueType RetVT, - ISD::NodeType Opcode, - unsigned Op0, unsigned Op1); - - /// FastEmit_ri - This method is called by target-independent code - /// to request that an instruction with the given type, opcode, and - /// register and immediate operands be emitted. - /// - virtual unsigned FastEmit_ri(MVT::SimpleValueType VT, - MVT::SimpleValueType RetVT, - ISD::NodeType Opcode, - unsigned Op0, uint64_t Imm); - - /// FastEmit_rf - This method is called by target-independent code - /// to request that an instruction with the given type, opcode, and - /// register and floating-point immediate operands be emitted. - /// - virtual unsigned FastEmit_rf(MVT::SimpleValueType VT, - MVT::SimpleValueType RetVT, - ISD::NodeType Opcode, - unsigned Op0, ConstantFP *FPImm); - - /// FastEmit_rri - This method is called by target-independent code - /// to request that an instruction with the given type, opcode, and - /// register and immediate operands be emitted. - /// - virtual unsigned FastEmit_rri(MVT::SimpleValueType VT, - MVT::SimpleValueType RetVT, - ISD::NodeType Opcode, - unsigned Op0, unsigned Op1, uint64_t Imm); - - /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries - /// to emit an instruction with an immediate operand using FastEmit_ri. - /// If that fails, it materializes the immediate into a register and try - /// FastEmit_rr instead. - unsigned FastEmit_ri_(MVT::SimpleValueType VT, - ISD::NodeType Opcode, - unsigned Op0, uint64_t Imm, - MVT::SimpleValueType ImmType); - - /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries - /// to emit an instruction with an immediate operand using FastEmit_rf. - /// If that fails, it materializes the immediate into a register and try - /// FastEmit_rr instead. - unsigned FastEmit_rf_(MVT::SimpleValueType VT, - ISD::NodeType Opcode, - unsigned Op0, ConstantFP *FPImm, - MVT::SimpleValueType ImmType); + /// This method is called by target-independent code when the normal FastISel + /// process fails to select an instruction. This gives targets a chance to + /// emit code for anything that doesn't fit into FastISel's framework. It + /// returns true if it was successful. + virtual bool + TargetSelectInstruction(const Instruction *I) = 0; - /// FastEmit_i - This method is called by target-independent code - /// to request that an instruction with the given type, opcode, and - /// immediate operand be emitted. - virtual unsigned FastEmit_i(MVT::SimpleValueType VT, - MVT::SimpleValueType RetVT, - ISD::NodeType Opcode, + /// This method is called by target-independent code to do target specific + /// argument lowering. It returns true if it was successful. + virtual bool FastLowerArguments(); + + /// This method is called by target-independent code to request that an + /// instruction with the given type and opcode be emitted. + virtual unsigned FastEmit_(MVT VT, + MVT RetVT, + unsigned Opcode); + + /// This method is called by target-independent code to request that an + /// instruction with the given type, opcode, and register operand be emitted. + virtual unsigned FastEmit_r(MVT VT, + MVT RetVT, + unsigned Opcode, + unsigned Op0, bool Op0IsKill); + + /// This method is called by target-independent code to request that an + /// instruction with the given type, opcode, and register operands be emitted. + virtual unsigned FastEmit_rr(MVT VT, + MVT RetVT, + unsigned Opcode, + unsigned Op0, bool Op0IsKill, + unsigned Op1, bool Op1IsKill); + + /// This method is called by target-independent code to request that an + /// instruction with the given type, opcode, and register and immediate + /// operands be emitted. + virtual unsigned FastEmit_ri(MVT VT, + MVT RetVT, + unsigned Opcode, + unsigned Op0, bool Op0IsKill, + uint64_t Imm); + + /// This method is called by target-independent code to request that an + /// instruction with the given type, opcode, and register and floating-point + /// immediate operands be emitted. + virtual unsigned FastEmit_rf(MVT VT, + MVT RetVT, + unsigned Opcode, + unsigned Op0, bool Op0IsKill, + const ConstantFP *FPImm); + + /// This method is called by target-independent code to request that an + /// instruction with the given type, opcode, and register and immediate + /// operands be emitted. + virtual unsigned FastEmit_rri(MVT VT, + MVT RetVT, + unsigned Opcode, + unsigned Op0, bool Op0IsKill, + unsigned Op1, bool Op1IsKill, + uint64_t Imm); + + /// \brief This method is a wrapper of FastEmit_ri. + /// + /// It first tries to emit an instruction with an immediate operand using + /// FastEmit_ri. If that fails, it materializes the immediate into a register + /// and try FastEmit_rr instead. + unsigned FastEmit_ri_(MVT VT, + unsigned Opcode, + unsigned Op0, bool Op0IsKill, + uint64_t Imm, MVT ImmType); + + /// This method is called by target-independent code to request that an + /// instruction with the given type, opcode, and immediate operand be emitted. + virtual unsigned FastEmit_i(MVT VT, + MVT RetVT, + unsigned Opcode, uint64_t Imm); - /// FastEmit_f - This method is called by target-independent code - /// to request that an instruction with the given type, opcode, and - /// floating-point immediate operand be emitted. - virtual unsigned FastEmit_f(MVT::SimpleValueType VT, - MVT::SimpleValueType RetVT, - ISD::NodeType Opcode, - ConstantFP *FPImm); + /// This method is called by target-independent code to request that an + /// instruction with the given type, opcode, and floating-point immediate + /// operand be emitted. + virtual unsigned FastEmit_f(MVT VT, + MVT RetVT, + unsigned Opcode, + const ConstantFP *FPImm); - /// FastEmitInst_ - Emit a MachineInstr with no operands and a - /// result register in the given register class. - /// + /// Emit a MachineInstr with no operands and a result register in the given + /// register class. unsigned FastEmitInst_(unsigned MachineInstOpcode, const TargetRegisterClass *RC); - /// FastEmitInst_r - Emit a MachineInstr with one register operand - /// and a result register in the given register class. - /// + /// Emit a MachineInstr with one register operand and a result register in the + /// given register class. unsigned FastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0); + unsigned Op0, bool Op0IsKill); - /// FastEmitInst_rr - Emit a MachineInstr with two register operands - /// and a result register in the given register class. - /// + /// Emit a MachineInstr with two register operands and a result register in + /// the given register class. unsigned FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0, unsigned Op1); + unsigned Op0, bool Op0IsKill, + unsigned Op1, bool Op1IsKill); - /// FastEmitInst_ri - Emit a MachineInstr with two register operands - /// and a result register in the given register class. - /// + /// Emit a MachineInstr with three register operands and a result register in + /// the given register class. + unsigned FastEmitInst_rrr(unsigned MachineInstOpcode, + const TargetRegisterClass *RC, + unsigned Op0, bool Op0IsKill, + unsigned Op1, bool Op1IsKill, + unsigned Op2, bool Op2IsKill); + + /// Emit a MachineInstr with a register operand, an immediate, and a result + /// register in the given register class. unsigned FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0, uint64_t Imm); + unsigned Op0, bool Op0IsKill, + uint64_t Imm); - /// FastEmitInst_rf - Emit a MachineInstr with two register operands - /// and a result register in the given register class. - /// + /// Emit a MachineInstr with one register operand and two immediate operands. + unsigned FastEmitInst_rii(unsigned MachineInstOpcode, + const TargetRegisterClass *RC, + unsigned Op0, bool Op0IsKill, + uint64_t Imm1, uint64_t Imm2); + + /// Emit a MachineInstr with two register operands and a result register in + /// the given register class. unsigned FastEmitInst_rf(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0, ConstantFP *FPImm); + unsigned Op0, bool Op0IsKill, + const ConstantFP *FPImm); - /// FastEmitInst_rri - Emit a MachineInstr with two register operands, - /// an immediate, and a result register in the given register class. - /// + /// Emit a MachineInstr with two register operands, an immediate, and a result + /// register in the given register class. unsigned FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0, unsigned Op1, uint64_t Imm); - - /// FastEmitInst_i - Emit a MachineInstr with a single immediate - /// operand, and a result register in the given register class. + unsigned Op0, bool Op0IsKill, + unsigned Op1, bool Op1IsKill, + uint64_t Imm); + + /// Emit a MachineInstr with two register operands, two immediates operands, + /// and a result register in the given register class. + unsigned FastEmitInst_rrii(unsigned MachineInstOpcode, + const TargetRegisterClass *RC, + unsigned Op0, bool Op0IsKill, + unsigned Op1, bool Op1IsKill, + uint64_t Imm1, uint64_t Imm2); + + /// Emit a MachineInstr with a single immediate operand, and a result register + /// in the given register class. unsigned FastEmitInst_i(unsigned MachineInstrOpcode, const TargetRegisterClass *RC, uint64_t Imm); - /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg - /// from a specified index of a superregister. - unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx); + /// Emit a MachineInstr with a two immediate operands. + unsigned FastEmitInst_ii(unsigned MachineInstrOpcode, + const TargetRegisterClass *RC, + uint64_t Imm1, uint64_t Imm2); + + /// Emit a MachineInstr for an extract_subreg from a specified index of a + /// superregister to a specified type. + unsigned FastEmitInst_extractsubreg(MVT RetVT, + unsigned Op0, bool Op0IsKill, + uint32_t Idx); + + /// Emit MachineInstrs to compute the value of Op with all but the least + /// significant bit set to zero. + unsigned FastEmitZExtFromI1(MVT VT, + unsigned Op0, bool Op0IsKill); - /// FastEmitBranch - Emit an unconditional branch to the given block, - /// unless it is the immediate (fall-through) successor, and update - /// the CFG. - void FastEmitBranch(MachineBasicBlock *MBB); + /// Emit an unconditional branch to the given block, unless it is the + /// immediate (fall-through) successor, and update the CFG. + void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL); - void UpdateValueMap(Value* I, unsigned Reg); + void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1); unsigned createResultReg(const TargetRegisterClass *RC); - - /// TargetMaterializeConstant - Emit a constant in a register using - /// target-specific logic, such as constant pool loads. - virtual unsigned TargetMaterializeConstant(Constant* C) { + + /// Try to constrain Op so that it is usable by argument OpNum of the provided + /// MCInstrDesc. If this fails, create a new virtual register in the correct + /// class and COPY the value there. + unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op, + unsigned OpNum); + + /// Emit a constant in a register using target-specific logic, such as + /// constant pool loads. + virtual unsigned TargetMaterializeConstant(const Constant* C) { + return 0; + } + + /// Emit an alloca address in a register using target-specific logic. + virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) { return 0; } - /// TargetMaterializeAlloca - Emit an alloca address in a register using - /// target-specific logic. - virtual unsigned TargetMaterializeAlloca(AllocaInst* C) { + virtual unsigned TargetMaterializeFloatZero(const ConstantFP* CF) { return 0; } + /// \brief Check if \c Add is an add that can be safely folded into \c GEP. + /// + /// \c Add can be folded into \c GEP if: + /// - \c Add is an add, + /// - \c Add's size matches \c GEP's, + /// - \c Add is in the same basic block as \c GEP, and + /// - \c Add has a constant operand. + bool canFoldAddIntoGEP(const User *GEP, const Value *Add); + + /// Test whether the given value has exactly one use. + bool hasTrivialKill(const Value *V) const; + + /// \brief Create a machine mem operand from the given instruction. + MachineMemOperand *createMachineMemOperandFor(const Instruction *I) const; + private: - bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode); + bool SelectBinaryOp(const User *I, unsigned ISDOpcode); - bool SelectGetElementPtr(User *I); + bool SelectFNeg(const User *I); - bool SelectCall(User *I); + bool SelectGetElementPtr(const User *I); - bool SelectBitCast(User *I); - - bool SelectCast(User *I, ISD::NodeType Opcode); + bool SelectCall(const User *I); + + bool SelectBitCast(const User *I); + + bool SelectCast(const User *I, unsigned Opcode); + + bool SelectExtractValue(const User *I); + + bool SelectInsertValue(const User *I); + + /// \brief Handle PHI nodes in successor blocks. + /// + /// Emit code to ensure constants are copied into registers when needed. + /// Remember the virtual registers that need to be added to the Machine PHI + /// nodes as input. We cannot just directly add them, because expansion might + /// result in multiple MBB's for one BB. As such, the start of the BB might + /// correspond to a different MBB than the end. + bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB); + + /// Helper for getRegForVale. This function is called when the value isn't + /// already available in a register and must be materialized with new + /// instructions. + unsigned materializeRegForValue(const Value *V, MVT VT); + + /// Clears LocalValueMap and moves the area for the new local variables to the + /// beginning of the block. It helps to avoid spilling cached variables across + /// heavy instructions like calls. + void flushLocalValueMap(); + + bool addStackMapLiveVars(SmallVectorImpl &Ops, + const CallInst *CI, unsigned StartIdx); }; }