X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FCodeGen%2FLiveStackAnalysis.h;h=3ffbe3d775b42ebbb6828d3383c64fcf1c101d91;hb=512052a88e8f1b0bb874f741fe72fb398d12ffbc;hp=b4808ab1f1d472f7f1f0f34fee81420ec18a5f64;hpb=cf0db29df20d9c665da7e82bb261bdd7cf7f1b2b;p=oota-llvm.git

diff --git a/include/llvm/CodeGen/LiveStackAnalysis.h b/include/llvm/CodeGen/LiveStackAnalysis.h
index b4808ab1f1d..3ffbe3d775b 100644
--- a/include/llvm/CodeGen/LiveStackAnalysis.h
+++ b/include/llvm/CodeGen/LiveStackAnalysis.h
@@ -25,76 +25,74 @@
 
 namespace llvm {
 
-  class LiveStacks : public MachineFunctionPass {
-    const TargetRegisterInfo *TRI;
-
-    /// Special pool allocator for VNInfo's (LiveInterval val#).
-    ///
-    VNInfo::Allocator VNInfoAllocator;
-
-    /// S2IMap - Stack slot indices to live interval mapping.
-    ///
-    typedef std::unordered_map<int, LiveInterval> SS2IntervalMap;
-    SS2IntervalMap S2IMap;
-
-    /// S2RCMap - Stack slot indices to register class mapping.
-    std::map<int, const TargetRegisterClass*> S2RCMap;
-    
-  public:
-    static char ID; // Pass identification, replacement for typeid
-    LiveStacks() : MachineFunctionPass(ID) {
-      initializeLiveStacksPass(*PassRegistry::getPassRegistry());
-    }
-
-    typedef SS2IntervalMap::iterator iterator;
-    typedef SS2IntervalMap::const_iterator const_iterator;
-    const_iterator begin() const { return S2IMap.begin(); }
-    const_iterator end() const { return S2IMap.end(); }
-    iterator begin() { return S2IMap.begin(); }
-    iterator end() { return S2IMap.end(); }
-
-    unsigned getNumIntervals() const { return (unsigned)S2IMap.size(); }
-
-    LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
-
-    LiveInterval &getInterval(int Slot) {
-      assert(Slot >= 0 && "Spill slot indice must be >= 0");
-      SS2IntervalMap::iterator I = S2IMap.find(Slot);
-      assert(I != S2IMap.end() && "Interval does not exist for stack slot");
-      return I->second;
-    }
-
-    const LiveInterval &getInterval(int Slot) const {
-      assert(Slot >= 0 && "Spill slot indice must be >= 0");
-      SS2IntervalMap::const_iterator I = S2IMap.find(Slot);
-      assert(I != S2IMap.end() && "Interval does not exist for stack slot");
-      return I->second;
-    }
-
-    bool hasInterval(int Slot) const {
-      return S2IMap.count(Slot);
-    }
-
-    const TargetRegisterClass *getIntervalRegClass(int Slot) const {
-      assert(Slot >= 0 && "Spill slot indice must be >= 0");
-      std::map<int, const TargetRegisterClass*>::const_iterator
-        I = S2RCMap.find(Slot);
-      assert(I != S2RCMap.end() &&
-             "Register class info does not exist for stack slot");
-      return I->second;
-    }
-
-    VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
-
-    void getAnalysisUsage(AnalysisUsage &AU) const override;
-    void releaseMemory() override;
-
-    /// runOnMachineFunction - pass entry point
-    bool runOnMachineFunction(MachineFunction&) override;
-
-    /// print - Implement the dump method.
-    void print(raw_ostream &O, const Module* = nullptr) const override;
-  };
-} // namespace llvm
+class LiveStacks : public MachineFunctionPass {
+  const TargetRegisterInfo *TRI;
+
+  /// Special pool allocator for VNInfo's (LiveInterval val#).
+  ///
+  VNInfo::Allocator VNInfoAllocator;
+
+  /// S2IMap - Stack slot indices to live interval mapping.
+  ///
+  typedef std::unordered_map<int, LiveInterval> SS2IntervalMap;
+  SS2IntervalMap S2IMap;
+
+  /// S2RCMap - Stack slot indices to register class mapping.
+  std::map<int, const TargetRegisterClass *> S2RCMap;
+
+public:
+  static char ID; // Pass identification, replacement for typeid
+  LiveStacks() : MachineFunctionPass(ID) {
+    initializeLiveStacksPass(*PassRegistry::getPassRegistry());
+  }
+
+  typedef SS2IntervalMap::iterator iterator;
+  typedef SS2IntervalMap::const_iterator const_iterator;
+  const_iterator begin() const { return S2IMap.begin(); }
+  const_iterator end() const { return S2IMap.end(); }
+  iterator begin() { return S2IMap.begin(); }
+  iterator end() { return S2IMap.end(); }
+
+  unsigned getNumIntervals() const { return (unsigned)S2IMap.size(); }
+
+  LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
+
+  LiveInterval &getInterval(int Slot) {
+    assert(Slot >= 0 && "Spill slot indice must be >= 0");
+    SS2IntervalMap::iterator I = S2IMap.find(Slot);
+    assert(I != S2IMap.end() && "Interval does not exist for stack slot");
+    return I->second;
+  }
+
+  const LiveInterval &getInterval(int Slot) const {
+    assert(Slot >= 0 && "Spill slot indice must be >= 0");
+    SS2IntervalMap::const_iterator I = S2IMap.find(Slot);
+    assert(I != S2IMap.end() && "Interval does not exist for stack slot");
+    return I->second;
+  }
+
+  bool hasInterval(int Slot) const { return S2IMap.count(Slot); }
+
+  const TargetRegisterClass *getIntervalRegClass(int Slot) const {
+    assert(Slot >= 0 && "Spill slot indice must be >= 0");
+    std::map<int, const TargetRegisterClass *>::const_iterator I =
+        S2RCMap.find(Slot);
+    assert(I != S2RCMap.end() &&
+           "Register class info does not exist for stack slot");
+    return I->second;
+  }
+
+  VNInfo::Allocator &getVNInfoAllocator() { return VNInfoAllocator; }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override;
+  void releaseMemory() override;
+
+  /// runOnMachineFunction - pass entry point
+  bool runOnMachineFunction(MachineFunction &) override;
+
+  /// print - Implement the dump method.
+  void print(raw_ostream &O, const Module * = nullptr) const override;
+};
+}
 
 #endif /* LLVM_CODEGEN_LIVESTACK_ANALYSIS_H */