X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FCodeGen%2FLiveVariables.h;h=55b97dc3e71d94306be66c173fb50e4f56a36c3a;hb=0e99876efe5c2cbea63ec91c74ec923c3fd193e5;hp=737dabc1ae73ef6693d57051fcc61e148f285515;hpb=4c214d2bf0da92a7973bb7902c0d6d055b1fa991;p=oota-llvm.git diff --git a/include/llvm/CodeGen/LiveVariables.h b/include/llvm/CodeGen/LiveVariables.h index 737dabc1ae7..55b97dc3e71 100644 --- a/include/llvm/CodeGen/LiveVariables.h +++ b/include/llvm/CodeGen/LiveVariables.h @@ -1,20 +1,20 @@ //===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// //===----------------------------------------------------------------------===// -// -// This file implements the LiveVariable analysis pass. For each machine +// +// This file implements the LiveVariables analysis pass. For each machine // instruction in the function, this pass calculates the set of registers that // are immediately dead after the instruction (i.e., the instruction calculates // the value, but it is never used) and the set of registers that are used by // the instruction, but are never used after the instruction (i.e., they are // killed). // -// This class computes live variables using are sparse implementation based on +// This class computes live variables using a sparse implementation based on // the machine code SSA form. This class computes live variable information for // each virtual and _register allocatable_ physical register in a function. It // uses the dominance properties of SSA form to efficiently compute live @@ -23,194 +23,287 @@ // to resolve physical register lifetimes in each basic block). If a physical // register is not register allocatable, it is not tracked. This is useful for // things like the stack pointer and condition codes. -// +// //===----------------------------------------------------------------------===// #ifndef LLVM_CODEGEN_LIVEVARIABLES_H #define LLVM_CODEGEN_LIVEVARIABLES_H +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/IndexedMap.h" +#include "llvm/ADT/SmallSet.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/SparseBitVector.h" #include "llvm/CodeGen/MachineFunctionPass.h" -#include +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/Target/TargetRegisterInfo.h" namespace llvm { -class MRegisterInfo; +class MachineBasicBlock; +class MachineRegisterInfo; class LiveVariables : public MachineFunctionPass { public: - struct VarInfo { - /// DefBlock - The basic block which defines this value... - MachineBasicBlock *DefBlock; - MachineInstr *DefInst; + static char ID; // Pass identification, replacement for typeid + LiveVariables() : MachineFunctionPass(ID) { + initializeLiveVariablesPass(*PassRegistry::getPassRegistry()); + } - /// AliveBlocks - Set of blocks of which this value is alive completely + /// VarInfo - This represents the regions where a virtual register is live in + /// the program. We represent this with three different pieces of + /// information: the set of blocks in which the instruction is live + /// throughout, the set of blocks in which the instruction is actually used, + /// and the set of non-phi instructions that are the last users of the value. + /// + /// In the common case where a value is defined and killed in the same block, + /// There is one killing instruction, and AliveBlocks is empty. + /// + /// Otherwise, the value is live out of the block. If the value is live + /// throughout any blocks, these blocks are listed in AliveBlocks. Blocks + /// where the liveness range ends are not included in AliveBlocks, instead + /// being captured by the Kills set. In these blocks, the value is live into + /// the block (unless the value is defined and killed in the same block) and + /// lives until the specified instruction. Note that there cannot ever be a + /// value whose Kills set contains two instructions from the same basic block. + /// + /// PHI nodes complicate things a bit. If a PHI node is the last user of a + /// value in one of its predecessor blocks, it is not listed in the kills set, + /// but does include the predecessor block in the AliveBlocks set (unless that + /// block also defines the value). This leads to the (perfectly sensical) + /// situation where a value is defined in a block, and the last use is a phi + /// node in the successor. In this case, AliveBlocks is empty (the value is + /// not live across any blocks) and Kills is empty (phi nodes are not + /// included). This is sensical because the value must be live to the end of + /// the block, but is not live in any successor blocks. + struct VarInfo { + /// AliveBlocks - Set of blocks in which this value is alive completely /// through. This is a bit set which uses the basic block number as an /// index. /// - std::vector AliveBlocks; + SparseBitVector<> AliveBlocks; - /// Kills - List of MachineBasicblock's which contain the last use of this - /// virtual register (kill it). This also includes the specific instruction - /// which kills the value. + /// Kills - List of MachineInstruction's which are the last use of this + /// virtual register (kill it) in their basic block. /// - std::vector > Kills; - - VarInfo() : DefBlock(0), DefInst(0) {} - - /// removeKill - Delete a kill corresponding to the specified machine instr - void removeKill(MachineInstr *MI) { - for (unsigned i = 0; ; ++i) { - assert(i < Kills.size() && "Machine instr is not a kill!"); - if (Kills[i].second == MI) { - Kills.erase(Kills.begin()+i); - return; - } - } + std::vector Kills; + + /// removeKill - Delete a kill corresponding to the specified + /// machine instruction. Returns true if there was a kill + /// corresponding to this instruction, false otherwise. + bool removeKill(MachineInstr *MI) { + std::vector::iterator + I = std::find(Kills.begin(), Kills.end(), MI); + if (I == Kills.end()) + return false; + Kills.erase(I); + return true; } + + /// findKill - Find a kill instruction in MBB. Return NULL if none is found. + MachineInstr *findKill(const MachineBasicBlock *MBB) const; + + /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through + /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in + /// MBB, it is not considered live in. + bool isLiveIn(const MachineBasicBlock &MBB, + unsigned Reg, + MachineRegisterInfo &MRI); + + void dump() const; }; private: /// VirtRegInfo - This list is a mapping from virtual register number to - /// variable information. FirstVirtualRegister is subtracted from the virtual - /// register number before indexing into this list. + /// variable information. /// - std::vector VirtRegInfo; + IndexedMap VirtRegInfo; - /// RegistersKilled - This multimap keeps track of all of the registers that - /// are dead immediately after an instruction reads its operands. If an - /// instruction does not have an entry in this map, it kills no registers. - /// - std::multimap RegistersKilled; + /// PHIJoins - list of virtual registers that are PHI joins. These registers + /// may have multiple definitions, and they require special handling when + /// building live intervals. + SparseBitVector<> PHIJoins; - /// RegistersDead - This multimap keeps track of all of the registers that are - /// dead immediately after an instruction executes, which are not dead after - /// the operands are evaluated. In practice, this only contains registers - /// which are defined by an instruction, but never used. - /// - std::multimap RegistersDead; +private: // Intermediate data structures + MachineFunction *MF; - /// AllocatablePhysicalRegisters - This vector keeps track of which registers - /// are actually register allocatable by the target machine. We can not track - /// liveness for values that are not in this set. - /// - std::vector AllocatablePhysicalRegisters; + MachineRegisterInfo* MRI; -private: // Intermediate data structures + const TargetRegisterInfo *TRI; - /// BBMap - Maps LLVM basic blocks to their corresponding machine basic block. - /// This also provides a numbering of the basic blocks in the function. - std::map > BBMap; - - const MRegisterInfo *RegInfo; + // PhysRegInfo - Keep track of which instruction was the last def of a + // physical register. This is a purely local property, because all physical + // register references are presumed dead across basic blocks. + std::vector PhysRegDef; - MachineInstr **PhysRegInfo; - bool *PhysRegUsed; + // PhysRegInfo - Keep track of which instruction was the last use of a + // physical register. This is a purely local property, because all physical + // register references are presumed dead across basic blocks. + std::vector PhysRegUse; -public: + std::vector> PHIVarInfo; - virtual bool runOnMachineFunction(MachineFunction &MF); + // DistanceMap - Keep track the distance of a MI from the start of the + // current basic block. + DenseMap DistanceMap; - /// getMachineBasicBlockIndex - Turn a MachineBasicBlock into an index number - /// suitable for use with VarInfo's. - /// - const std::pair - &getMachineBasicBlockInfo(MachineBasicBlock *MBB) const; - const std::pair - &getBasicBlockInfo(const BasicBlock *BB) const { - return BBMap.find(BB)->second; - } + /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the + /// uses. Pay special attention to the sub-register uses which may come below + /// the last use of the whole register. + bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI); + /// HandleRegMask - Call HandlePhysRegKill for all registers clobbered by Mask. + void HandleRegMask(const MachineOperand&); - /// killed_iterator - Iterate over registers killed by a machine instruction - /// - typedef std::multimap::iterator killed_iterator; - - /// killed_begin/end - Get access to the range of registers killed by a - /// machine instruction. - killed_iterator killed_begin(MachineInstr *MI) { - return RegistersKilled.lower_bound(MI); - } - killed_iterator killed_end(MachineInstr *MI) { - return RegistersKilled.upper_bound(MI); - } - std::pair - killed_range(MachineInstr *MI) { - return RegistersKilled.equal_range(MI); - } + void HandlePhysRegUse(unsigned Reg, MachineInstr *MI); + void HandlePhysRegDef(unsigned Reg, MachineInstr *MI, + SmallVectorImpl &Defs); + void UpdatePhysRegDefs(MachineInstr *MI, SmallVectorImpl &Defs); - killed_iterator dead_begin(MachineInstr *MI) { - return RegistersDead.lower_bound(MI); - } - killed_iterator dead_end(MachineInstr *MI) { - return RegistersDead.upper_bound(MI); - } - std::pair - dead_range(MachineInstr *MI) { - return RegistersDead.equal_range(MI); - } + /// FindLastRefOrPartRef - Return the last reference or partial reference of + /// the specified register. + MachineInstr *FindLastRefOrPartRef(unsigned Reg); + + /// FindLastPartialDef - Return the last partial def of the specified + /// register. Also returns the sub-registers that're defined by the + /// instruction. + MachineInstr *FindLastPartialDef(unsigned Reg, + SmallSet &PartDefRegs); + + /// analyzePHINodes - Gather information about the PHI nodes in here. In + /// particular, we want to map the variable information of a virtual + /// register which is used in a PHI node. We map that to the BB the vreg + /// is coming from. + void analyzePHINodes(const MachineFunction& Fn); + + void runOnInstr(MachineInstr *MI, SmallVectorImpl &Defs); + + void runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs); +public: + + bool runOnMachineFunction(MachineFunction &MF) override; + + /// RegisterDefIsDead - Return true if the specified instruction defines the + /// specified register, but that definition is dead. + bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const; //===--------------------------------------------------------------------===// // API to update live variable information + /// replaceKillInstruction - Update register kill info by replacing a kill + /// instruction with a new one. + void replaceKillInstruction(unsigned Reg, MachineInstr *OldMI, + MachineInstr *NewMI); + /// addVirtualRegisterKilled - Add information about the fact that the /// specified register is killed after being used by the specified - /// instruction. - /// - void addVirtualRegisterKilled(unsigned IncomingReg, MachineBasicBlock *MBB, - MachineInstr *MI) { - RegistersKilled.insert(std::make_pair(MI, IncomingReg)); - getVarInfo(IncomingReg).Kills.push_back(std::make_pair(MBB, MI)); + /// instruction. If AddIfNotFound is true, add a implicit operand if it's + /// not found. + void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI, + bool AddIfNotFound = false) { + if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound)) + getVarInfo(IncomingReg).Kills.push_back(MI); } - /// removeVirtualRegistersKilled - Remove all of the specified killed - /// registers from the live variable information. - void removeVirtualRegistersKilled(killed_iterator B, killed_iterator E) { - for (killed_iterator I = B; I != E; ++I) // Remove VarInfo entries... - getVarInfo(I->second).removeKill(I->first); - RegistersKilled.erase(B, E); + /// removeVirtualRegisterKilled - Remove the specified kill of the virtual + /// register from the live variable information. Returns true if the + /// variable was marked as killed by the specified instruction, + /// false otherwise. + bool removeVirtualRegisterKilled(unsigned reg, MachineInstr *MI) { + if (!getVarInfo(reg).removeKill(MI)) + return false; + + bool Removed = false; + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI->getOperand(i); + if (MO.isReg() && MO.isKill() && MO.getReg() == reg) { + MO.setIsKill(false); + Removed = true; + break; + } + } + + assert(Removed && "Register is not used by this instruction!"); + (void)Removed; + return true; } + /// removeVirtualRegistersKilled - Remove all killed info for the specified + /// instruction. + void removeVirtualRegistersKilled(MachineInstr *MI); + /// addVirtualRegisterDead - Add information about the fact that the specified - /// register is dead after being used by the specified instruction. - /// - void addVirtualRegisterDead(unsigned IncomingReg, MachineBasicBlock *MBB, - MachineInstr *MI) { - RegistersDead.insert(std::make_pair(MI, IncomingReg)); - getVarInfo(IncomingReg).Kills.push_back(std::make_pair(MBB, MI)); + /// register is dead after being used by the specified instruction. If + /// AddIfNotFound is true, add a implicit operand if it's not found. + void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI, + bool AddIfNotFound = false) { + if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound)) + getVarInfo(IncomingReg).Kills.push_back(MI); } - /// removeVirtualRegistersKilled - Remove all of the specified killed - /// registers from the live variable information. - void removeVirtualRegistersDead(killed_iterator B, killed_iterator E) { - for (killed_iterator I = B; I != E; ++I) // Remove VarInfo entries... - getVarInfo(I->second).removeKill(I->first); - RegistersDead.erase(B, E); + /// removeVirtualRegisterDead - Remove the specified kill of the virtual + /// register from the live variable information. Returns true if the + /// variable was marked dead at the specified instruction, false + /// otherwise. + bool removeVirtualRegisterDead(unsigned reg, MachineInstr *MI) { + if (!getVarInfo(reg).removeKill(MI)) + return false; + + bool Removed = false; + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI->getOperand(i); + if (MO.isReg() && MO.isDef() && MO.getReg() == reg) { + MO.setIsDead(false); + Removed = true; + break; + } + } + assert(Removed && "Register is not defined by this instruction!"); + (void)Removed; + return true; } - virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AU.setPreservesAll(); - } + void getAnalysisUsage(AnalysisUsage &AU) const override; - virtual void releaseMemory() { + void releaseMemory() override { VirtRegInfo.clear(); - RegistersKilled.clear(); - RegistersDead.clear(); - BBMap.clear(); } /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL /// register. VarInfo &getVarInfo(unsigned RegIdx); - const std::vector& getAllocatablePhysicalRegisters() const { - return AllocatablePhysicalRegisters; + void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock, + MachineBasicBlock *BB); + void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock, + MachineBasicBlock *BB, + std::vector &WorkList); + void HandleVirtRegDef(unsigned reg, MachineInstr *MI); + void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, + MachineInstr *MI); + + bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) { + return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI); } - void MarkVirtRegAliveInBlock(VarInfo &VRInfo, const BasicBlock *BB); - void HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB, - MachineInstr *MI); - void HandlePhysRegUse(unsigned Reg, MachineInstr *MI); - void HandlePhysRegDef(unsigned Reg, MachineInstr *MI); + /// isLiveOut - Determine if Reg is live out from MBB, when not considering + /// PHI nodes. This means that Reg is either killed by a successor block or + /// passed through one. + bool isLiveOut(unsigned Reg, const MachineBasicBlock &MBB); + + /// addNewBlock - Add a new basic block BB between DomBB and SuccBB. All + /// variables that are live out of DomBB and live into SuccBB will be marked + /// as passing live through BB. This method assumes that the machine code is + /// still in SSA form. + void addNewBlock(MachineBasicBlock *BB, + MachineBasicBlock *DomBB, + MachineBasicBlock *SuccBB); + + /// isPHIJoin - Return true if Reg is a phi join register. + bool isPHIJoin(unsigned Reg) { return PHIJoins.test(Reg); } + + /// setPHIJoin - Mark Reg as a phi join register. + void setPHIJoin(unsigned Reg) { PHIJoins.set(Reg); } }; } // End llvm namespace