X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FCodeGen%2FScheduleDAG.h;h=e90bceb7be50f656df299c28f8adcd97ad7fd9ba;hb=3cc6243ddfdba3ad64035b919c88b09773a60880;hp=18aa97a9694394e1244f4569b71f3df497dd592e;hpb=4c8c83022b501759d8559e224c84ae2a9921ba41;p=oota-llvm.git diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index 18aa97a9694..e90bceb7be5 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -17,13 +17,11 @@ #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/ADT/BitVector.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/GraphTraits.h" #include "llvm/ADT/SmallSet.h" namespace llvm { - struct InstrStage; struct SUnit; class MachineConstantPool; class MachineFunction; @@ -31,6 +29,7 @@ namespace llvm { class MachineRegisterInfo; class MachineInstr; class TargetRegisterInfo; + class ScheduleDAG; class SelectionDAG; class SelectionDAGISel; class TargetInstrInfo; @@ -93,8 +92,10 @@ namespace llvm { /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or /// a group of nodes flagged together. struct SUnit { + private: SDNode *Node; // Representative node. - SmallVector FlaggedNodes;// All nodes flagged to Node. + MachineInstr *Instr; // Alternatively, a MachineInstr. + public: SUnit *OrigNode; // If not this, the node from which // this node was cloned. @@ -111,8 +112,8 @@ namespace llvm { unsigned NodeNum; // Entry # of node in the node vector. unsigned NodeQueueId; // Queue id of node. unsigned short Latency; // Node latency. - short NumPreds; // # of preds. - short NumSuccs; // # of sucss. + short NumPreds; // # of non-control preds. + short NumSuccs; // # of non-control sucss. short NumPredsLeft; // # of preds not scheduled. short NumSuccsLeft; // # of succs not scheduled. bool isTwoAddress : 1; // Is a two-address instruction. @@ -128,14 +129,54 @@ namespace llvm { const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null. const TargetRegisterClass *CopySrcRC; + /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent + /// an SDNode and any nodes flagged to it. SUnit(SDNode *node, unsigned nodenum) - : Node(node), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), Latency(0), - NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), + : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), + Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), + isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), + isPending(false), isAvailable(false), isScheduled(false), + CycleBound(0), Cycle(0), Depth(0), Height(0), + CopyDstRC(NULL), CopySrcRC(NULL) {} + + /// SUnit - Construct an SUnit for post-regalloc scheduling to represent + /// a MachineInstr. + SUnit(MachineInstr *instr, unsigned nodenum) + : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), + Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), isPending(false), isAvailable(false), isScheduled(false), CycleBound(0), Cycle(0), Depth(0), Height(0), CopyDstRC(NULL), CopySrcRC(NULL) {} + /// setNode - Assign the representative SDNode for this SUnit. + /// This may be used during pre-regalloc scheduling. + void setNode(SDNode *N) { + assert(!Instr && "Setting SDNode of SUnit with MachineInstr!"); + Node = N; + } + + /// getNode - Return the representative SDNode for this SUnit. + /// This may be used during pre-regalloc scheduling. + SDNode *getNode() const { + assert(!Instr && "Reading SDNode of SUnit with MachineInstr!"); + return Node; + } + + /// setInstr - Assign the instruction for the SUnit. + /// This may be used during post-regalloc scheduling. + void setInstr(MachineInstr *MI) { + assert(!Node && "Setting MachineInstr of SUnit with SDNode!"); + Instr = MI; + } + + /// getInstr - Return the representative MachineInstr for this SUnit. + /// This may be used during post-regalloc scheduling. + MachineInstr *getInstr() const { + assert(!Node && "Reading MachineInstr of SUnit with SDNode!"); + return Instr; + } + /// addPred - This adds the specified node as a pred of the current node if /// not already. This returns true if this is a new pred. bool addPred(SUnit *N, bool isCtrl, bool isSpecial, @@ -199,8 +240,8 @@ namespace llvm { return false; } - void dump(const SelectionDAG *G) const; - void dumpAll(const SelectionDAG *G) const; + void dump(const ScheduleDAG *G) const; + void dumpAll(const ScheduleDAG *G) const; }; //===--------------------------------------------------------------------===// @@ -215,8 +256,7 @@ namespace llvm { public: virtual ~SchedulingPriorityQueue() {} - virtual void initNodes(DenseMap &SUMap, - std::vector &SUnits) = 0; + virtual void initNodes(std::vector &SUnits) = 0; virtual void addNode(const SUnit *SU) = 0; virtual void updateNode(const SUnit *SU) = 0; virtual void releaseState() = 0; @@ -231,8 +271,9 @@ namespace llvm { virtual void remove(SUnit *SU) = 0; /// ScheduledNode - As each node is scheduled, this method is invoked. This - /// allows the priority function to adjust the priority of node that have - /// already been emitted. + /// allows the priority function to adjust the priority of related + /// unscheduled nodes, for example. + /// virtual void ScheduledNode(SUnit *) {} virtual void UnscheduledNode(SUnit *) {} @@ -240,7 +281,7 @@ namespace llvm { class ScheduleDAG { public: - SelectionDAG &DAG; // DAG of the current basic block + SelectionDAG *DAG; // DAG of the current basic block MachineBasicBlock *BB; // Current basic block const TargetMachine &TM; // Target processor const TargetInstrInfo *TII; // Target instruction information @@ -251,11 +292,10 @@ namespace llvm { MachineConstantPool *ConstPool; // Target constant pool std::vector Sequence; // The schedule. Null SUnit*'s // represent noop instructions. - DenseMap SUnitMap; // SDNode to SUnit mapping (n -> n). std::vector SUnits; // The scheduling units. SmallSet CommuteSet; // Nodes that should be commuted. - ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb, + ScheduleDAG(SelectionDAG *dag, MachineBasicBlock *bb, const TargetMachine &tm); virtual ~ScheduleDAG() {} @@ -267,7 +307,7 @@ namespace llvm { /// Run - perform scheduling. /// - MachineBasicBlock *Run(); + void Run(); /// isPassiveNode - Return true if the node is a non-scheduled leaf. /// @@ -294,6 +334,14 @@ namespace llvm { return &SUnits.back(); } + /// NewSUnit - Creates a new SUnit and return a ptr to it. + /// + SUnit *NewSUnit(MachineInstr *MI) { + SUnits.push_back(SUnit(MI, (unsigned)SUnits.size())); + SUnits.back().OrigNode = &SUnits.back(); + return &SUnits.back(); + } + /// Clone - Creates a clone of the specified SUnit. It does not copy the /// predecessors / successors info nor the temporary scheduling states. SUnit *Clone(SUnit *N); @@ -332,38 +380,38 @@ namespace llvm { /// register number for the results of the node. /// void EmitNode(SDNode *Node, bool IsClone, - DenseMap &VRBaseMap); + DenseMap &VRBaseMap); /// EmitNoop - Emit a noop instruction. /// void EmitNoop(); - void EmitSchedule(); + MachineBasicBlock *EmitSchedule(); void dumpSchedule() const; - /// Schedule - Order nodes according to selected style. + /// Schedule - Order nodes according to selected style, filling + /// in the Sequence member. /// - virtual void Schedule() {} + virtual void Schedule() = 0; private: /// EmitSubregNode - Generate machine code for subreg nodes. /// void EmitSubregNode(SDNode *Node, - DenseMap &VRBaseMap); + DenseMap &VRBaseMap); /// getVR - Return the virtual register corresponding to the specified result /// of the specified node. - unsigned getVR(SDOperand Op, DenseMap &VRBaseMap); + unsigned getVR(SDValue Op, DenseMap &VRBaseMap); /// getDstOfCopyToRegUse - If the only use of the specified result number of /// node is a CopyToReg, return its destination register. Return 0 otherwise. unsigned getDstOfOnlyCopyToRegUse(SDNode *Node, unsigned ResNo) const; - void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum, + void AddOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum, const TargetInstrDesc *II, - DenseMap &VRBaseMap); - + DenseMap &VRBaseMap); void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO); void EmitCrossRCCopy(SUnit *SU, DenseMap &VRBaseMap); @@ -372,11 +420,11 @@ namespace llvm { /// implicit physical register output. void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, unsigned SrcReg, - DenseMap &VRBaseMap); + DenseMap &VRBaseMap); void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, const TargetInstrDesc &II, - DenseMap &VRBaseMap); + DenseMap &VRBaseMap); /// EmitLiveInCopy - Emit a copy for a live in physical register. If the /// physical register has only a single copy use, then coalesced the copy @@ -391,31 +439,52 @@ namespace llvm { /// and if it has live ins that need to be copied into vregs, emit the /// copies into the top of the block. void EmitLiveInCopies(MachineBasicBlock *MBB); + + /// BuildSchedUnitsFromMBB - Build SUnits from the MachineBasicBlock. + /// This SUnit graph is similar to the pre-regalloc SUnit graph, but represents + /// MachineInstrs directly instead of SDNodes. + void BuildSchedUnitsFromMBB(); }; /// createBURRListDAGScheduler - This creates a bottom up register usage /// reduction list scheduler. ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, - MachineBasicBlock *BB); + const TargetMachine *TM, + MachineBasicBlock *BB, + bool Fast); /// createTDRRListDAGScheduler - This creates a top down register usage /// reduction list scheduler. ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, - MachineBasicBlock *BB); + const TargetMachine *TM, + MachineBasicBlock *BB, + bool Fast); /// createTDListDAGScheduler - This creates a top-down list scheduler with /// a hazard recognizer. ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, - MachineBasicBlock *BB); + const TargetMachine *TM, + MachineBasicBlock *BB, + bool Fast); + /// createFastDAGScheduler - This creates a "fast" scheduler. + /// + ScheduleDAG *createFastDAGScheduler(SelectionDAGISel *IS, + SelectionDAG *DAG, + const TargetMachine *TM, + MachineBasicBlock *BB, + bool Fast); + /// createDefaultScheduler - This creates an instruction scheduler appropriate /// for the target. ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, - MachineBasicBlock *BB); + const TargetMachine *TM, + MachineBasicBlock *BB, + bool Fast); class SUnitIterator : public forward_iterator { SUnit *Node;