X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FCodeGen%2FSelectionDAGISel.h;h=82542d1bb4964e5b234ab3c3f8d187df2715d6b6;hb=fc718542a3e73558af9c0272b0eea67a189e5397;hp=497040d55b6b86f7d49202e9cbae5c7001cadb62;hpb=1997473cf72957d0e70322e2fe6fe2ab141c58a6;p=oota-llvm.git

diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index 497040d55b6..82542d1bb49 100644
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -23,28 +23,31 @@
 namespace llvm {
   class SelectionDAGLowering;
   class SDOperand;
-  class SSARegMap;
+  class MachineRegisterInfo;
   class MachineBasicBlock;
   class MachineFunction;
   class MachineInstr;
   class TargetLowering;
   class FunctionLoweringInfo;
   class HazardRecognizer;
+  class CollectorMetadata;
  
 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
 /// pattern-matching instruction selectors.
 class SelectionDAGISel : public FunctionPass {
 public:
   TargetLowering &TLI;
-  SSARegMap *RegMap;
+  MachineRegisterInfo *RegInfo;
   SelectionDAG *CurDAG;
   MachineBasicBlock *BB;
+  AliasAnalysis *AA;
   std::vector<SDNode*> TopOrder;
   unsigned DAGSize;
+  CollectorMetadata *GCI;
   static char ID;
 
   explicit SelectionDAGISel(TargetLowering &tli) : 
-    FunctionPass((intptr_t)&ID), TLI(tli), DAGSize(0) {}
+    FunctionPass((intptr_t)&ID), TLI(tli), DAGSize(0), GCI(0) {}
   
   TargetLowering &getTargetLowering() { return TLI; }
 
@@ -74,7 +77,9 @@ public:
 
   /// CanBeFoldedBy - Returns true if the specific operand node N of U can be
   /// folded during instruction selection that starts at Root?
-  virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) { return true;}
+  virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const {
+    return true;
+  }
   
   /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
   /// to use for this target when scheduling the DAG.
@@ -102,7 +107,7 @@ public:
   };
   struct JumpTable {
     JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
-              MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {};
+              MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
     
     /// Reg - the virtual register containing the index of the jump table entry
     //. to jump to.
@@ -118,7 +123,7 @@ public:
   struct JumpTableHeader {
     JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
                     bool E = false):
-      First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {};
+      First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
     uint64_t First;
     uint64_t Last;
     Value *SValue;
@@ -129,7 +134,7 @@ public:
 
   struct BitTestCase {
     BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
-      Mask(M), ThisBB(T), TargetBB(Tr) { };
+      Mask(M), ThisBB(T), TargetBB(Tr) { }
     uint64_t Mask;
     MachineBasicBlock* ThisBB;
     MachineBasicBlock* TargetBB;
@@ -143,7 +148,7 @@ public:
                  MachineBasicBlock* P, MachineBasicBlock* D,
                  const BitTestInfo& C):
       First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
-      Parent(P), Default(D), Cases(C) { };
+      Parent(P), Default(D), Cases(C) { }
     uint64_t First;
     uint64_t Range;
     Value  *SValue;
@@ -164,8 +169,10 @@ protected:
                                      SelectionDAG &DAG);
 
   // Calls to these predicates are generated by tblgen.
-  bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, int64_t DesiredMaskS);  
-  bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, int64_t DesiredMaskS);  
+  bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
+                    int64_t DesiredMaskS) const;
+  bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
+                    int64_t DesiredMaskS) const;
   
 private:
   void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,