X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FCodeGen%2FSelectionDAGISel.h;h=82542d1bb4964e5b234ab3c3f8d187df2715d6b6;hb=fc718542a3e73558af9c0272b0eea67a189e5397;hp=6ffe86a41e81fd896075eec37da5583df6eec012;hpb=423c2260f95883f7c84ac962e58ac66c3a11efac;p=oota-llvm.git diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h index 6ffe86a41e8..82542d1bb49 100644 --- a/include/llvm/CodeGen/SelectionDAGISel.h +++ b/include/llvm/CodeGen/SelectionDAGISel.h @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -23,27 +23,31 @@ namespace llvm { class SelectionDAGLowering; class SDOperand; - class SSARegMap; + class MachineRegisterInfo; class MachineBasicBlock; class MachineFunction; class MachineInstr; class TargetLowering; class FunctionLoweringInfo; class HazardRecognizer; + class CollectorMetadata; /// SelectionDAGISel - This is the common base class used for SelectionDAG-based /// pattern-matching instruction selectors. class SelectionDAGISel : public FunctionPass { public: TargetLowering &TLI; - SSARegMap *RegMap; + MachineRegisterInfo *RegInfo; SelectionDAG *CurDAG; MachineBasicBlock *BB; + AliasAnalysis *AA; std::vector TopOrder; unsigned DAGSize; + CollectorMetadata *GCI; + static char ID; - explicit SelectionDAGISel(TargetLowering &tli) - : TLI(tli), DAGSize(0), JT(0,0,0,0) {} + explicit SelectionDAGISel(TargetLowering &tli) : + FunctionPass((intptr_t)&ID), TLI(tli), DAGSize(0), GCI(0) {} TargetLowering &getTargetLowering() { return TLI; } @@ -73,7 +77,9 @@ public: /// CanBeFoldedBy - Returns true if the specific operand node N of U can be /// folded during instruction selection that starts at Root? - virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) { return true;} + virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const { + return true; + } /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer /// to use for this target when scheduling the DAG. @@ -83,15 +89,17 @@ public: /// SDISel for the code generation of additional basic blocks needed by multi- /// case switch statements. struct CaseBlock { - CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, + CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle, MachineBasicBlock *truebb, MachineBasicBlock *falsebb, MachineBasicBlock *me) - : CC(cc), CmpLHS(cmplhs), CmpRHS(cmprhs), + : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs), TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {} // CC - the condition code to use for the case block's setcc node ISD::CondCode CC; - // CmpLHS/CmpRHS - The LHS/RHS of the comparison to emit. - Value *CmpLHS, *CmpRHS; + // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit. + // Emit by default LHS op RHS. MHS is used for range comparisons: + // If MHS is not null: (LHS <= MHS) and (MHS <= RHS). + Value *CmpLHS, *CmpMHS, *CmpRHS; // TrueBB/FalseBB - the block to branch to if the setcc is true/false. MachineBasicBlock *TrueBB, *FalseBB; // ThisBB - the block into which to emit the code for the setcc and branches @@ -99,19 +107,57 @@ public: }; struct JumpTable { JumpTable(unsigned R, unsigned J, MachineBasicBlock *M, - MachineBasicBlock *D) : Reg(R), JTI(J), MBB(M), Default(D) {} - // Reg - the virtual register containing the index of the jump table entry - // to jump to. + MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {} + + /// Reg - the virtual register containing the index of the jump table entry + //. to jump to. unsigned Reg; - // JTI - the JumpTableIndex for this jump table in the function. + /// JTI - the JumpTableIndex for this jump table in the function. unsigned JTI; - // MBB - the MBB into which to emit the code for the indirect jump. + /// MBB - the MBB into which to emit the code for the indirect jump. MachineBasicBlock *MBB; - // Default - the MBB of the default bb, which is a successor of the range - // check MBB. This is when updating PHI nodes in successors. + /// Default - the MBB of the default bb, which is a successor of the range + /// check MBB. This is when updating PHI nodes in successors. MachineBasicBlock *Default; }; + struct JumpTableHeader { + JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H, + bool E = false): + First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {} + uint64_t First; + uint64_t Last; + Value *SValue; + MachineBasicBlock *HeaderBB; + bool Emitted; + }; + typedef std::pair JumpTableBlock; + + struct BitTestCase { + BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr): + Mask(M), ThisBB(T), TargetBB(Tr) { } + uint64_t Mask; + MachineBasicBlock* ThisBB; + MachineBasicBlock* TargetBB; + }; + typedef SmallVector BitTestInfo; + + struct BitTestBlock { + BitTestBlock(uint64_t F, uint64_t R, Value* SV, + unsigned Rg, bool E, + MachineBasicBlock* P, MachineBasicBlock* D, + const BitTestInfo& C): + First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E), + Parent(P), Default(D), Cases(C) { } + uint64_t First; + uint64_t Range; + Value *SValue; + unsigned Reg; + bool Emitted; + MachineBasicBlock *Parent; + MachineBasicBlock *Default; + BitTestInfo Cases; + }; protected: /// Pick a safe ordering and emit instructions for each target node in the /// graph. @@ -123,8 +169,10 @@ protected: SelectionDAG &DAG); // Calls to these predicates are generated by tblgen. - bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, int64_t DesiredMaskS); - bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, int64_t DesiredMaskS); + bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, + int64_t DesiredMaskS) const; + bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, + int64_t DesiredMaskS) const; private: void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF, @@ -141,8 +189,11 @@ private: /// SwitchInst code generation information. std::vector SwitchCases; - /// JT - Record which holds necessary information for emitting a jump table - JumpTable JT; + /// JTCases - Vector of JumpTable structures which holds necessary information + /// for emitting a jump tables during SwitchInst code generation. + std::vector JTCases; + + std::vector BitTestCases; }; }