X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FMC%2FMCInst.h;h=e91c6a2e8ee7b1af18af62d005059f6df342d764;hb=96d58e64cfe88356f8be4ce622b829fbd9fb5908;hp=e34bc00ba98de40dd105701818916c354f62031e;hpb=475370b036a9e355b51c899465efc00532bb3c41;p=oota-llvm.git

diff --git a/include/llvm/MC/MCInst.h b/include/llvm/MC/MCInst.h
index e34bc00ba98..e91c6a2e8ee 100644
--- a/include/llvm/MC/MCInst.h
+++ b/include/llvm/MC/MCInst.h
@@ -13,13 +13,20 @@
 //
 //===----------------------------------------------------------------------===//
 
-
 #ifndef LLVM_MC_MCINST_H
 #define LLVM_MC_MCINST_H
 
 #include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/Support/DataTypes.h"
+#include "llvm/Support/SMLoc.h"
 
 namespace llvm {
+class raw_ostream;
+class MCAsmInfo;
+class MCInstPrinter;
+class MCExpr;
+class MCInst;
 
 /// MCOperand - Instances of this class represent operands of the MCInst class.
 /// This is a simple discriminated union.
@@ -27,22 +34,31 @@ class MCOperand {
   enum MachineOperandType {
     kInvalid,                 ///< Uninitialized.
     kRegister,                ///< Register operand.
-    kImmediate                ///< Immediate operand.
+    kImmediate,               ///< Immediate operand.
+    kFPImmediate,             ///< Floating-point immediate operand.
+    kExpr,                    ///< Relocatable immediate operand.
+    kInst                     ///< Sub-instruction operand.
   };
   unsigned char Kind;
-  
+
   union {
     unsigned RegVal;
-    uint64_t ImmVal;
+    int64_t ImmVal;
+    double FPImmVal;
+    const MCExpr *ExprVal;
+    const MCInst *InstVal;
   };
 public:
-  
-  MCOperand() : Kind(kInvalid) {}
-  MCOperand(const MCOperand &RHS) { *this = RHS; }
 
+  MCOperand() : Kind(kInvalid), FPImmVal(0.0) {}
+
+  bool isValid() const { return Kind != kInvalid; }
   bool isReg() const { return Kind == kRegister; }
   bool isImm() const { return Kind == kImmediate; }
-  
+  bool isFPImm() const { return Kind == kFPImmediate; }
+  bool isExpr() const { return Kind == kExpr; }
+  bool isInst() const { return Kind == kInst; }
+
   /// getReg - Returns the register number.
   unsigned getReg() const {
     assert(isReg() && "This is not a register operand!");
@@ -54,39 +70,134 @@ public:
     assert(isReg() && "This is not a register operand!");
     RegVal = Reg;
   }
-  
-  uint64_t getImm() const {
+
+  int64_t getImm() const {
     assert(isImm() && "This is not an immediate");
     return ImmVal;
   }
-  void setImm(uint64_t Val) {
+  void setImm(int64_t Val) {
     assert(isImm() && "This is not an immediate");
     ImmVal = Val;
   }
-  
-  void MakeReg(unsigned Reg) {
-    Kind = kRegister;
-    RegVal = Reg;
+
+  double getFPImm() const {
+    assert(isFPImm() && "This is not an FP immediate");
+    return FPImmVal;
   }
-  void MakeImm(uint64_t Val) {
-    Kind = kImmediate;
-    ImmVal = Val;
+
+  void setFPImm(double Val) {
+    assert(isFPImm() && "This is not an FP immediate");
+    FPImmVal = Val;
+  }
+
+  const MCExpr *getExpr() const {
+    assert(isExpr() && "This is not an expression");
+    return ExprVal;
+  }
+  void setExpr(const MCExpr *Val) {
+    assert(isExpr() && "This is not an expression");
+    ExprVal = Val;
+  }
+
+  const MCInst *getInst() const {
+    assert(isInst() && "This is not a sub-instruction");
+    return InstVal;
+  }
+  void setInst(const MCInst *Val) {
+    assert(isInst() && "This is not a sub-instruction");
+    InstVal = Val;
+  }
+
+  static MCOperand CreateReg(unsigned Reg) {
+    MCOperand Op;
+    Op.Kind = kRegister;
+    Op.RegVal = Reg;
+    return Op;
   }
+  static MCOperand CreateImm(int64_t Val) {
+    MCOperand Op;
+    Op.Kind = kImmediate;
+    Op.ImmVal = Val;
+    return Op;
+  }
+  static MCOperand CreateFPImm(double Val) {
+    MCOperand Op;
+    Op.Kind = kFPImmediate;
+    Op.FPImmVal = Val;
+    return Op;
+  }
+  static MCOperand CreateExpr(const MCExpr *Val) {
+    MCOperand Op;
+    Op.Kind = kExpr;
+    Op.ExprVal = Val;
+    return Op;
+  }
+  static MCOperand CreateInst(const MCInst *Val) {
+    MCOperand Op;
+    Op.Kind = kInst;
+    Op.InstVal = Val;
+    return Op;
+  }
+
+  void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
+  void dump() const;
 };
 
-  
+template <> struct isPodLike<MCOperand> { static const bool value = true; };
+
 /// MCInst - Instances of this class represent a single low-level machine
-/// instruction. 
+/// instruction.
 class MCInst {
   unsigned Opcode;
+  SMLoc Loc;
   SmallVector<MCOperand, 8> Operands;
 public:
-  MCInst() : Opcode(~0U) {}
-  
-  
-  
+  MCInst() : Opcode(0) {}
+
+  void setOpcode(unsigned Op) { Opcode = Op; }
+  unsigned getOpcode() const { return Opcode; }
+
+  void setLoc(SMLoc loc) { Loc = loc; }
+  SMLoc getLoc() const { return Loc; }
+
+  const MCOperand &getOperand(unsigned i) const { return Operands[i]; }
+  MCOperand &getOperand(unsigned i) { return Operands[i]; }
+  unsigned getNumOperands() const { return Operands.size(); }
+
+  void addOperand(const MCOperand &Op) {
+    Operands.push_back(Op);
+  }
+
+  void clear() { Operands.clear(); }
+  size_t size() { return Operands.size(); }
+
+  typedef SmallVector<MCOperand, 8>::iterator iterator;
+  iterator begin() { return Operands.begin(); }
+  iterator end()   { return Operands.end();   }
+  iterator insert(iterator I, const MCOperand &Op) {
+    return Operands.insert(I, Op);
+  }
+
+  void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
+  void dump() const;
+
+  /// \brief Dump the MCInst as prettily as possible using the additional MC
+  /// structures, if given. Operators are separated by the \p Separator
+  /// string.
+  void dump_pretty(raw_ostream &OS, const MCAsmInfo *MAI = 0,
+                   const MCInstPrinter *Printer = 0,
+                   StringRef Separator = " ") const;
 };
 
+inline raw_ostream& operator<<(raw_ostream &OS, const MCOperand &MO) {
+  MO.print(OS, 0);
+  return OS;
+}
+
+inline raw_ostream& operator<<(raw_ostream &OS, const MCInst &MI) {
+  MI.print(OS, 0);
+  return OS;
+}
 
 } // end namespace llvm