X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FObject%2FELFTypes.h;fp=include%2Fllvm%2FObject%2FELFTypes.h;h=287d3670678a6f114b58da06a3474c47093e90a3;hb=eda9f8aa7499b2f448d5d6d947b75a4fc240384b;hp=1952b9480d0199c9017e0d12624b881983727065;hpb=7b0f8fc600aea7f453c494e50cb3e53893c89769;p=oota-llvm.git diff --git a/include/llvm/Object/ELFTypes.h b/include/llvm/Object/ELFTypes.h index 1952b9480d0..287d3670678 100644 --- a/include/llvm/Object/ELFTypes.h +++ b/include/llvm/Object/ELFTypes.h @@ -489,6 +489,43 @@ struct Elf_Phdr_Impl > { Elf_Xword p_align; // Segment alignment constraint }; +// MIPS .reginfo section +template +struct Elf_Mips_RegInfo; + +template +struct Elf_Mips_RegInfo> { + LLVM_ELF_IMPORT_TYPES(TargetEndianness, MaxAlign, false) + Elf_Word ri_gprmask; // bit-mask of used general registers + Elf_Word ri_cprmask[4]; // bit-mask of used co-processor registers + Elf_Addr ri_gp_value; // gp register value +}; + +template +struct Elf_Mips_RegInfo> { + LLVM_ELF_IMPORT_TYPES(TargetEndianness, MaxAlign, true) + Elf_Word ri_gprmask; // bit-mask of used general registers + Elf_Word ri_pad; // unused padding field + Elf_Word ri_cprmask[4]; // bit-mask of used co-processor registers + Elf_Addr ri_gp_value; // gp register value +}; + +// .MIPS.options section +template struct Elf_Mips_Options { + LLVM_ELF_IMPORT_TYPES_ELFT(ELFT) + uint8_t kind; // Determines interpretation of variable part of descriptor + uint8_t size; // Byte size of descriptor, including this header + Elf_Half section; // Section header index of section affected, + // or 0 for global options + Elf_Word info; // Kind-specific information + + const Elf_Mips_RegInfo &getRegInfo() const { + assert(kind == llvm::ELF::ODK_REGINFO); + return *reinterpret_cast *>( + (const uint8_t *)this + sizeof(Elf_Mips_Options)); + } +}; + // .MIPS.abiflags section content template struct Elf_Mips_ABIFlags { LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)