X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FTarget%2FMRegisterInfo.h;h=2db4f2031bd7c47d17371e7101778f67fde96169;hb=c651e4c51e11feb58e6c12fee8a8f85631269f2f;hp=e0f0cd428ca7e99a3d07448600ea1d4f19525218;hpb=5e73d5bd2e98afda12fa69a7ea83050c69be0d34;p=oota-llvm.git diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h index e0f0cd428ca..2db4f2031bd 100644 --- a/include/llvm/Target/MRegisterInfo.h +++ b/include/llvm/Target/MRegisterInfo.h @@ -23,23 +23,32 @@ namespace llvm { -class Type; +class BitVector; +class CalleeSavedInfo; class MachineFunction; class MachineInstr; class MachineLocation; class MachineMove; +class RegScavenger; class TargetRegisterClass; -class CalleeSavedInfo; +class Type; /// TargetRegisterDesc - This record contains all of the information known about /// a particular register. The AliasSet field (if not null) contains a pointer /// to a Zero terminated array of registers that this register aliases. This is /// needed for architectures like X86 which have AL alias AX alias EAX. /// Registers that this does not apply to simply should set this to null. +/// The SubRegs field is a zero terminated array of registers that are +/// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX. +/// The SuperRegs field is a zero terminated array of registers that are +/// super-registers of the specific register, e.g. RAX, EAX, are sub-registers +/// of AX. /// struct TargetRegisterDesc { const char *Name; // Assembly language name for the register const unsigned *AliasSet; // Register Alias Set, described above + const unsigned *SubRegs; // Sub-register set, described above + const unsigned *SuperRegs; // Super-register set, described above }; class TargetRegisterClass { @@ -239,8 +248,10 @@ public: } /// getAllocatableSet - Returns a bitset indexed by register number - /// indicating if a register is allocatable or not. - std::vector getAllocatableSet(MachineFunction &MF) const; + /// indicating if a register is allocatable or not. If a register class is + /// specified, returns the subset for the class. + BitVector getAllocatableSet(MachineFunction &MF, + const TargetRegisterClass *RC = NULL) const; const TargetRegisterDesc &operator[](unsigned RegNo) const { assert(RegNo < NumRegs && @@ -263,6 +274,22 @@ public: return get(RegNo).AliasSet; } + /// getSubRegisters - Return the set of registers that are sub-registers of + /// the specified register, or a null list of there are none. The list + /// returned is zero terminated. + /// + const unsigned *getSubRegisters(unsigned RegNo) const { + return get(RegNo).SubRegs; + } + + /// getSuperRegisters - Return the set of registers that are super-registers + /// of the specified register, or a null list of there are none. The list + /// returned is zero terminated. + /// + const unsigned *getSuperRegisters(unsigned RegNo) const { + return get(RegNo).SuperRegs; + } + /// getName - Return the symbolic target specific name for the specified /// physical register. const char *getName(unsigned RegNo) const { @@ -283,6 +310,33 @@ public: return false; } + /// regsOverlap - Returns true if the two registers are equal or alias + /// each other. The registers may be virtual register. + bool regsOverlap(unsigned regA, unsigned regB) const { + if (regA == regB) + return true; + + if (isVirtualRegister(regA) || isVirtualRegister(regB)) + return false; + return areAliases(regA, regB); + } + + /// isSubRegister - Returns true if regB is a sub-register of regA. + /// + bool isSubRegister(unsigned regA, unsigned regB) const { + for (const unsigned *SR = getSubRegisters(regA); *SR; ++SR) + if (*SR == regB) return true; + return false; + } + + /// isSuperRegister - Returns true if regB is a super-register of regA. + /// + bool isSuperRegister(unsigned regA, unsigned regB) const { + for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR) + if (*SR == regB) return true; + return false; + } + /// getCalleeSavedRegs - Return a null-terminated list of all of the /// callee saved registers on this target. The register should be in the /// order of desired callee-save stack frame offset. The first register is @@ -294,6 +348,12 @@ public: /// length of this list match the getCalleeSaveRegs() list. virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const =0; + /// getReservedRegs - Returns a bitset indexed by physical register number + /// indicating if a register is a special register that has particular uses and + /// should be considered unavailable at all times, e.g. SP, RA. This is used by + /// register scavenger to determine what registers are free. + virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; + //===--------------------------------------------------------------------===// // Register Class Information // @@ -355,6 +415,13 @@ public: unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *RC) const = 0; + /// reMaterialize - Re-issue the specified 'original' instruction at the + /// specific location targeting a new destination register. + virtual void reMaterialize(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, + const MachineInstr *Orig) const = 0; + /// foldMemoryOperand - Attempt to fold a load or store of the /// specified stack slot into the specified machine instruction for /// the specified operand. If this is possible, a new instruction @@ -367,6 +434,18 @@ public: return 0; } + /// targetHandlesStackFrameRounding - Returns true if the target is responsible + /// for rounding up the stack frame (probably at emitPrologue time). + virtual bool targetHandlesStackFrameRounding() const { + return false; + } + + /// requiresRegisterScavenging - returns true if the target requires (and + /// can make use of) the register scavenger. + virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { + return false; + } + /// hasFP - Return true if the specified function should have a dedicated frame /// pointer register. For most targets this is true only if the function has /// variable sized allocas or if frame pointer elimination is disabled. @@ -402,7 +481,9 @@ public: /// processFunctionBeforeCalleeSavedScan - This method is called immediately /// before PrologEpilogInserter scans the physical registers used to determine /// what callee saved registers should be spilled. This method is optional. - virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF) const { + virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, + RegScavenger *RS = NULL) const { + } /// processFunctionBeforeFrameFinalized - This method is called immediately @@ -421,7 +502,8 @@ public: /// finished product. The return value is the number of instructions /// added to (negative if removed from) the basic block. /// - virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0; + virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, + RegScavenger *RS = NULL) const = 0; /// emitProlog/emitEpilog - These methods insert prolog and epilog code into /// the function. The return value is the number of instructions @@ -445,7 +527,7 @@ public: /// getRARegister - This method should return the register where the return /// address can be found. virtual unsigned getRARegister() const = 0; - + /// getLocation - This method should return the actual location of a frame /// variable given the frame index. The location is returned in ML. /// Subclasses should override this method for special handling of frame @@ -459,7 +541,7 @@ public: virtual void getInitialFrameState(std::vector &Moves) const; }; -// This is useful when building DenseMaps keyed on virtual registers +// This is useful when building IndexedMaps keyed on virtual registers struct VirtReg2IndexFunctor : std::unary_function { unsigned operator()(unsigned Reg) const { return Reg - MRegisterInfo::FirstVirtualRegister;