X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FTarget%2FTarget.td;h=24be2b10416cf597e1aa92933950f25062f26567;hb=2ca6b3c37498eebf1f729f85cee03aa38ea5bc65;hp=ca551e586a5128046c4cd9d7a7157bb6d2dd531f;hpb=ca561ffcf320e9dbfafcac5efcee81471f3259c3;p=oota-llvm.git diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index ca551e586a5..24be2b10416 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -1,10 +1,10 @@ //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// -// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file defines the target-independent interfaces which should be @@ -22,32 +22,33 @@ include "llvm/Intrinsics.td" class RegisterClass; // Forward def // SubRegIndex - Use instances of SubRegIndex to identify subregisters. -class SubRegIndex { +class SubRegIndex comps = []> { + string Namespace = ""; + + // ComposedOf - A list of two SubRegIndex instances, [A, B]. + // This indicates that this SubRegIndex is the result of composing A and B. + list ComposedOf = comps; +} + +// RegAltNameIndex - The alternate name set to use for register operands of +// this register class when printing. +class RegAltNameIndex { string Namespace = ""; } +def NoRegAltName : RegAltNameIndex; // Register - You should define one instance of this class for each register // in the target machine. String n will become the "name" of the register. -class Register { +class Register altNames = []> { string Namespace = ""; string AsmName = n; - - // SpillSize - If this value is set to a non-zero value, it is the size in - // bits of the spill slot required to hold this register. If this value is - // set to zero, the information is inferred from any register classes the - // register belongs to. - int SpillSize = 0; - - // SpillAlignment - This value is used to specify the alignment required for - // spilling the register. Like SpillSize, this should only be explicitly - // specified if the register is not in a register class. - int SpillAlignment = 0; + list AltNames = altNames; // Aliases - A list of registers that this register overlaps with. A read or // modification of this register can potentially read or modify the aliased // registers. list Aliases = []; - + // SubRegs - A list of registers that are parts of this register. Note these // are "immediate" sub-registers and the registers within the list do not // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], @@ -59,17 +60,9 @@ class Register { // SubRegs. list SubRegIndices = []; - // CompositeIndices - Specify subreg indices that don't correspond directly to - // a register in SubRegs and are not inherited. The following formats are - // supported: - // - // (a) Identity - Reg:a == Reg - // (a b) Alias - Reg:a == Reg:b - // (a b,c) Composite - Reg:a == (Reg:b):c - // - // This can be used to disambiguate a sub-sub-register that exists in more - // than one subregister and other weird stuff. - list CompositeIndices = []; + // RegAltNameIndices - The alternate name indices which are valid for this + // register. + list RegAltNameIndices = []; // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. // These values can be determined by locating the .h file in the @@ -78,30 +71,53 @@ class Register { // -1 indicates that the gcc number is undefined and -2 that register number // is invalid for this mode/flavour. list DwarfNumbers = []; + + // CostPerUse - Additional cost of instructions using this register compared + // to other registers in its class. The register allocator will try to + // minimize the number of instructions using a register with a CostPerUse. + // This is used by the x86-64 and ARM Thumb targets where some registers + // require larger instruction encodings. + int CostPerUse = 0; + + // CoveredBySubRegs - When this bit is set, the value of this register is + // completely determined by the value of its sub-registers. For example, the + // x86 register AX is covered by its sub-registers AL and AH, but EAX is not + // covered by its sub-register AX. + bit CoveredBySubRegs = 0; + + // HWEncoding - The target specific hardware encoding for this register. + bits<16> HWEncoding = 0; } // RegisterWithSubRegs - This can be used to define instances of Register which // need to specify sub-registers. // List "subregs" specifies which registers are sub-registers to this one. This // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. -// This allows the code generator to be careful not to put two values with +// This allows the code generator to be careful not to put two values with // overlapping live ranges into registers which alias. class RegisterWithSubRegs subregs> : Register { let SubRegs = subregs; } +// DAGOperand - An empty base class that unifies RegisterClass's and other forms +// of Operand's that are legal as type qualifiers in DAG patterns. This should +// only ever be used for defining multiclasses that are polymorphic over both +// RegisterClass's and other Operand's. +class DAGOperand { } + // RegisterClass - Now that all of the registers are defined, and aliases // between registers are defined, specify which registers belong to which // register classes. This also defines the default allocation order of // registers by register allocators. // class RegisterClass regTypes, int alignment, - list regList> { + dag regList, RegAltNameIndex idx = NoRegAltName> + : DAGOperand { string Namespace = namespace; // RegType - Specify the list ValueType of the registers in this register // class. Note that all registers in a register class must have the same - // ValueTypes. This is a list because some targets permit storing different + // ValueTypes. This is a list because some targets permit storing different // types in same register, for example vector values with 128-bit total size, // but different count/size of items, like SSE on x86. // @@ -126,17 +142,104 @@ class RegisterClass regTypes, int alignment, // allocation_order_* method are not specified, this also defines the order of // allocation used by the register allocator. // - list MemberList = regList; - - // SubRegClasses - Specify the register class of subregisters as a list of - // dags: (RegClass SubRegIndex, SubRegindex, ...) - list SubRegClasses = []; + dag MemberList = regList; + + // AltNameIndex - The alternate register name to use when printing operands + // of this register class. Every register in the register class must have + // a valid alternate name for the given index. + RegAltNameIndex altNameIndex = idx; + + // isAllocatable - Specify that the register class can be used for virtual + // registers and register allocation. Some register classes are only used to + // model instruction operand constraints, and should have isAllocatable = 0. + bit isAllocatable = 1; + + // AltOrders - List of alternative allocation orders. The default order is + // MemberList itself, and that is good enough for most targets since the + // register allocators automatically remove reserved registers and move + // callee-saved registers to the end. + list AltOrders = []; + + // AltOrderSelect - The body of a function that selects the allocation order + // to use in a given machine function. The code will be inserted in a + // function like this: + // + // static inline unsigned f(const MachineFunction &MF) { ... } + // + // The function should return 0 to select the default order defined by + // MemberList, 1 to select the first AltOrders entry and so on. + code AltOrderSelect = [{}]; +} + +// The memberList in a RegisterClass is a dag of set operations. TableGen +// evaluates these set operations and expand them into register lists. These +// are the most common operation, see test/TableGen/SetTheory.td for more +// examples of what is possible: +// +// (add R0, R1, R2) - Set Union. Each argument can be an individual register, a +// register class, or a sub-expression. This is also the way to simply list +// registers. +// +// (sub GPR, SP) - Set difference. Subtract the last arguments from the first. +// +// (and GPR, CSR) - Set intersection. All registers from the first set that are +// also in the second set. +// +// (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of +// numbered registers. Takes an optional 4th operand which is a stride to use +// when generating the sequence. +// +// (shl GPR, 4) - Remove the first N elements. +// +// (trunc GPR, 4) - Truncate after the first N elements. +// +// (rotl GPR, 1) - Rotate N places to the left. +// +// (rotr GPR, 1) - Rotate N places to the right. +// +// (decimate GPR, 2) - Pick every N'th element, starting with the first. +// +// (interleave A, B, ...) - Interleave the elements from each argument list. +// +// All of these operators work on ordered sets, not lists. That means +// duplicates are removed from sub-expressions. + +// Set operators. The rest is defined in TargetSelectionDAG.td. +def sequence; +def decimate; +def interleave; - // MethodProtos/MethodBodies - These members can be used to insert arbitrary - // code into a generated register class. The normal usage of this is to - // overload virtual methods. - code MethodProtos = [{}]; - code MethodBodies = [{}]; +// RegisterTuples - Automatically generate super-registers by forming tuples of +// sub-registers. This is useful for modeling register sequence constraints +// with pseudo-registers that are larger than the architectural registers. +// +// The sub-register lists are zipped together: +// +// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>; +// +// Generates the same registers as: +// +// let SubRegIndices = [sube, subo] in { +// def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>; +// def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>; +// } +// +// The generated pseudo-registers inherit super-classes and fields from their +// first sub-register. Most fields from the Register class are inferred, and +// the AsmName and Dwarf numbers are cleared. +// +// RegisterTuples instances can be used in other set operations to form +// register classes and so on. This is the only way of using the generated +// registers. +class RegisterTuples Indices, list Regs> { + // SubRegs - N lists of registers to be zipped up. Super-registers are + // synthesized from the first element of each SubRegs list, the second + // element and so on. + list SubRegs = Regs; + + // SubRegIndices - N SubRegIndex instances. This provides the names of the + // sub-registers in the synthesized super-registers. + list SubRegIndices = Indices; } @@ -150,11 +253,19 @@ class DwarfRegNum Numbers> { // These values can be determined by locating the .h file in the // directory llvmgcc/gcc/config// and looking for REGISTER_NAMES. The // order of these names correspond to the enumeration used by gcc. A value of - // -1 indicates that the gcc number is undefined and -2 that register number is - // invalid for this mode/flavour. + // -1 indicates that the gcc number is undefined and -2 that register number + // is invalid for this mode/flavour. list DwarfNumbers = Numbers; } +// DwarfRegAlias - This class declares that a given register uses the same dwarf +// numbers as another one. This is useful for making it clear that the two +// registers do have the same number. It also lets us build a mapping +// from dwarf register number to llvm register. +class DwarfRegAlias { + Register DwarfAlias = reg; +} + //===----------------------------------------------------------------------===// // Pull in the common support for scheduling // @@ -187,7 +298,16 @@ class Instruction { // code. list Predicates = []; - // Code size. + // Size - Size of encoded instruction, or zero if the size cannot be determined + // from the opcode. + int Size = 0; + + // DecoderNamespace - The "namespace" in which this instruction exists, on + // targets like ARM which multiple ISA namespaces exist. + string DecoderNamespace = ""; + + // Code size, for instruction selection. + // FIXME: What does this actually mean? int CodeSize = 0; // Added complexity passed onto matching pattern. @@ -198,12 +318,14 @@ class Instruction { bit isReturn = 0; // Is this instruction a return instruction? bit isBranch = 0; // Is this instruction a branch instruction? bit isIndirectBranch = 0; // Is this instruction an indirect branch? + bit isCompare = 0; // Is this instruction a comparison instruction? + bit isMoveImm = 0; // Is this instruction a move immediate instruction? + bit isBitcast = 0; // Is this instruction a bitcast instruction? bit isBarrier = 0; // Can control flow fall through this instruction? bit isCall = 0; // Is this instruction a call instruction? bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? bit mayLoad = 0; // Is it possible for this inst to read memory? bit mayStore = 0; // Is it possible for this inst to write memory? - bit isTwoAddress = 0; // Is this a two address instruction? bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? bit isCommutable = 0; // Is this 3 operand instruction commutable? bit isTerminator = 0; // Is this part of the terminator for a basic block? @@ -211,11 +333,15 @@ class Instruction { bit isPredicable = 0; // Is this instruction predicable? bit hasDelaySlot = 0; // Does this instruction have an delay slot? bit usesCustomInserter = 0; // Pseudo instr needing special help. + bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook. bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? + bit isPseudo = 0; // Is this instruction a pseudo-instruction? + // If so, won't have encoding information for + // the [MC]CodeEmitter stuff. // Side effect flags - When set, the flags have these meanings: // @@ -230,6 +356,20 @@ class Instruction { // Is this instruction a "real" instruction (with a distinct machine // encoding), or is it a pseudo instruction used for codegen modeling // purposes. + // FIXME: For now this is distinct from isPseudo, above, as code-gen-only + // instructions can (and often do) still have encoding information + // associated with them. Once we've migrated all of them over to true + // pseudo-instructions that are lowered to real instructions prior to + // the printer/emitter, we can remove this attribute and just use isPseudo. + // + // The intended use is: + // isPseudo: Does not have encoding information and should be expanded, + // at the latest, during lowering to MCInst. + // + // isCodeGenOnly: Does have encoding information and can go through to the + // CodeEmitter unchanged, but duplicates a canonical instruction + // definition's encoding and should be ignored when constructing the + // assembler match tables. bit isCodeGenOnly = 0; // Is this instruction a pseudo instruction for use by the assembler parser. @@ -243,28 +383,71 @@ class Instruction { /// be encoded into the output machineinstr. string DisableEncoding = ""; + string PostEncoderMethod = ""; + string DecoderMethod = ""; + /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. - bits<32> TSFlags = 0; + bits<64> TSFlags = 0; + + ///@name Assembler Parser Support + ///@{ + + string AsmMatchConverter = ""; + + /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a + /// two-operand matcher inst-alias for a three operand instruction. + /// For example, the arm instruction "add r3, r3, r5" can be written + /// as "add r3, r5". The constraint is of the same form as a tied-operand + /// constraint. For example, "$Rn = $Rd". + string TwoOperandAliasConstraint = ""; + + ///@} +} + +/// PseudoInstExpansion - Expansion information for a pseudo-instruction. +/// Which instruction it expands to and how the operands map from the +/// pseudo. +class PseudoInstExpansion { + dag ResultInst = Result; // The instruction to generate. + bit isPseudo = 1; } /// Predicates - These are extra conditionals which are turned into instruction /// selector matching code. Currently each predicate is just a string. class Predicate { string CondString = cond; + + /// AssemblerMatcherPredicate - If this feature can be used by the assembler + /// matcher, this is true. Targets should set this by inheriting their + /// feature from the AssemblerPredicate class in addition to Predicate. + bit AssemblerMatcherPredicate = 0; + + /// AssemblerCondString - Name of the subtarget feature being tested used + /// as alternative condition string used for assembler matcher. + /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". + /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". + /// It can also list multiple features separated by ",". + /// e.g. "ModeThumb,FeatureThumb2" is translated to + /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". + string AssemblerCondString = ""; + + /// PredicateName - User-level name to use for the predicate. Mainly for use + /// in diagnostics such as missing feature errors in the asm matcher. + string PredicateName = ""; } /// NoHonorSignDependentRounding - This predicate is true if support for /// sign-dependent-rounding is not enabled. def NoHonorSignDependentRounding - : Predicate<"!HonorSignDependentRoundingFPMath()">; + : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">; class Requires preds> { list Predicates = preds; } -/// ops definition - This is just a simple marker used to identify the operands -/// list for an instruction. outs and ins are identical both syntatically and -/// semantically, they are used to define def operands and use operands to +/// ops definition - This is just a simple marker used to identify the operand +/// list for an instruction. outs and ins are identical both syntactically and +/// semanticallyr; they are used to define def operands and use operands to /// improve readibility. This should be used like this: /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. def ops; @@ -326,19 +509,33 @@ class AsmOperandClass { /// signature should be: /// void addFooOperands(MCInst &Inst, unsigned N) const; string RenderMethod = ?; + + /// The name of the method on the target specific operand to call to custom + /// handle the operand parsing. This is useful when the operands do not relate + /// to immediates or registers and are very instruction specific (as flags to + /// set in a processor register, coprocessor number, ...). + string ParserMethod = ?; + + // The diagnostic type to present when referencing this operand in a + // match failure error message. By default, use a generic "invalid operand" + // diagnostic. The target AsmParser maps these codes to text. + string DiagnosticType = ""; } def ImmAsmOperand : AsmOperandClass { let Name = "Imm"; } - + /// Operand Types - These provide the built-in operand types that may be used /// by a target. Targets can optionally provide their own operand types as /// needed, though this should not be needed for RISC targets. -class Operand { +class Operand : DAGOperand { ValueType Type = ty; string PrintMethod = "printOperand"; + string EncoderMethod = ""; + string DecoderMethod = ""; string AsmOperandLowerMethod = ?; + string OperandType = "OPERAND_UNKNOWN"; dag MIOperandInfo = (ops); // ParserMatchClass - The "match class" that operands of this type fit @@ -352,6 +549,26 @@ class Operand { AsmOperandClass ParserMatchClass = ImmAsmOperand; } +class RegisterOperand + : DAGOperand { + // RegClass - The register class of the operand. + RegisterClass RegClass = regclass; + // PrintMethod - The target method to call to print register operands of + // this type. The method normally will just use an alt-name index to look + // up the name to print. Default to the generic printOperand(). + string PrintMethod = pm; + // ParserMatchClass - The "match class" that operands of this type fit + // in. Match classes are used to define the order in which instructions are + // match, to ensure that which instructions gets matched is deterministic. + // + // The target specific parser must be able to classify an parsed operand into + // a unique class, which does not partially overlap with any other classes. It + // can match a subset of some other class, in which case the AsmOperandClass + // should declare the other operand as one of its super classes. + AsmOperandClass ParserMatchClass; +} + +let OperandType = "OPERAND_IMMEDIATE" in { def i1imm : Operand; def i8imm : Operand; def i16imm : Operand; @@ -360,6 +577,7 @@ def i64imm : Operand; def f32imm : Operand; def f64imm : Operand; +} /// zero_reg definition - Special node to stand for the zero register. /// @@ -397,24 +615,24 @@ class InstrInfo { } // Standard Pseudo Instructions. -let isCodeGenOnly = 1 in { +// This list must match TargetOpcodes.h and CodeGenTarget.cpp. +// Only these instructions are allowed in the TargetOpcode namespace. +let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in { def PHI : Instruction { let OutOperandList = (outs); let InOperandList = (ins variable_ops); let AsmString = "PHINODE"; - let Namespace = "TargetOpcode"; } def INLINEASM : Instruction { let OutOperandList = (outs); let InOperandList = (ins variable_ops); let AsmString = ""; - let Namespace = "TargetOpcode"; + let neverHasSideEffects = 1; // Note side effect is encoded in an operand. } -def DBG_LABEL : Instruction { +def PROLOG_LABEL : Instruction { let OutOperandList = (outs); let InOperandList = (ins i32imm:$id); let AsmString = ""; - let Namespace = "TargetOpcode"; let hasCtrlDep = 1; let isNotDuplicable = 1; } @@ -422,7 +640,6 @@ def EH_LABEL : Instruction { let OutOperandList = (outs); let InOperandList = (ins i32imm:$id); let AsmString = ""; - let Namespace = "TargetOpcode"; let hasCtrlDep = 1; let isNotDuplicable = 1; } @@ -430,7 +647,6 @@ def GC_LABEL : Instruction { let OutOperandList = (outs); let InOperandList = (ins i32imm:$id); let AsmString = ""; - let Namespace = "TargetOpcode"; let hasCtrlDep = 1; let isNotDuplicable = 1; } @@ -438,21 +654,18 @@ def KILL : Instruction { let OutOperandList = (outs); let InOperandList = (ins variable_ops); let AsmString = ""; - let Namespace = "TargetOpcode"; let neverHasSideEffects = 1; } def EXTRACT_SUBREG : Instruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); let AsmString = ""; - let Namespace = "TargetOpcode"; let neverHasSideEffects = 1; } def INSERT_SUBREG : Instruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); let AsmString = ""; - let Namespace = "TargetOpcode"; let neverHasSideEffects = 1; let Constraints = "$supersrc = $dst"; } @@ -460,7 +673,6 @@ def IMPLICIT_DEF : Instruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins); let AsmString = ""; - let Namespace = "TargetOpcode"; let neverHasSideEffects = 1; let isReMaterializable = 1; let isAsCheapAsAMove = 1; @@ -469,14 +681,12 @@ def SUBREG_TO_REG : Instruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); let AsmString = ""; - let Namespace = "TargetOpcode"; let neverHasSideEffects = 1; } def COPY_TO_REGCLASS : Instruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins unknown:$src, i32imm:$regclass); let AsmString = ""; - let Namespace = "TargetOpcode"; let neverHasSideEffects = 1; let isAsCheapAsAMove = 1; } @@ -484,18 +694,27 @@ def DBG_VALUE : Instruction { let OutOperandList = (outs); let InOperandList = (ins variable_ops); let AsmString = "DBG_VALUE"; - let Namespace = "TargetOpcode"; - let isAsCheapAsAMove = 1; + let neverHasSideEffects = 1; } - def REG_SEQUENCE : Instruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins variable_ops); let AsmString = ""; - let Namespace = "TargetOpcode"; let neverHasSideEffects = 1; let isAsCheapAsAMove = 1; } +def COPY : Instruction { + let OutOperandList = (outs unknown:$dst); + let InOperandList = (ins unknown:$src); + let AsmString = ""; + let neverHasSideEffects = 1; + let isAsCheapAsAMove = 1; +} +def BUNDLE : Instruction { + let OutOperandList = (outs); + let InOperandList = (ins variable_ops); + let AsmString = "BUNDLE"; +} } //===----------------------------------------------------------------------===// @@ -511,15 +730,19 @@ class AsmParser { // name. string AsmParserClassName = "AsmParser"; - // AsmParserInstCleanup - If non-empty, this is the name of a custom function on the - // AsmParser class to call on every matched instruction. This can be used to - // perform target specific instruction post-processing. + // AsmParserInstCleanup - If non-empty, this is the name of a custom member + // function of the AsmParser class to call on every matched instruction. + // This can be used to perform target specific instruction post-processing. string AsmParserInstCleanup = ""; +} +def DefaultAsmParser : AsmParser; - // MatchInstructionName - The name of the instruction matching function to - // generate. - string MatchInstructionName = "MatchInstruction"; - +//===----------------------------------------------------------------------===// +// AsmParserVariant - Subtargets can have multiple different assembly parsers +// (e.g. AT&T vs Intel syntax on X86 for example). This class can be +// implemented by targets to describe such variants. +// +class AsmParserVariant { // Variant - AsmParsers can be of multiple different variants. Variants are // used to support targets that need to parser multiple formats for the // assembly language. @@ -536,8 +759,67 @@ class AsmParser { // purposes of matching. string RegisterPrefix = ""; } -def DefaultAsmParser : AsmParser; +def DefaultAsmParserVariant : AsmParserVariant; + +/// AssemblerPredicate - This is a Predicate that can be used when the assembler +/// matches instructions and aliases. +class AssemblerPredicate { + bit AssemblerMatcherPredicate = 1; + string AssemblerCondString = cond; + string PredicateName = name; +} +/// TokenAlias - This class allows targets to define assembler token +/// operand aliases. That is, a token literal operand which is equivalent +/// to another, canonical, token literal. For example, ARM allows: +/// vmov.u32 s4, #0 -> vmov.i32, #0 +/// 'u32' is a more specific designator for the 32-bit integer type specifier +/// and is legal for any instruction which accepts 'i32' as a datatype suffix. +/// def : TokenAlias<".u32", ".i32">; +/// +/// This works by marking the match class of 'From' as a subclass of the +/// match class of 'To'. +class TokenAlias { + string FromToken = From; + string ToToken = To; +} + +/// MnemonicAlias - This class allows targets to define assembler mnemonic +/// aliases. This should be used when all forms of one mnemonic are accepted +/// with a different mnemonic. For example, X86 allows: +/// sal %al, 1 -> shl %al, 1 +/// sal %ax, %cl -> shl %ax, %cl +/// sal %eax, %cl -> shl %eax, %cl +/// etc. Though "sal" is accepted with many forms, all of them are directly +/// translated to a shl, so it can be handled with (in the case of X86, it +/// actually has one for each suffix as well): +/// def : MnemonicAlias<"sal", "shl">; +/// +/// Mnemonic aliases are mapped before any other translation in the match phase, +/// and do allow Requires predicates, e.g.: +/// +/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; +/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; +/// +class MnemonicAlias { + string FromMnemonic = From; + string ToMnemonic = To; + + // Predicates - Predicates that must be true for this remapping to happen. + list Predicates = []; +} + +/// InstAlias - This defines an alternate assembly syntax that is allowed to +/// match an instruction that has a different (more canonical) assembly +/// representation. +class InstAlias { + string AsmString = Asm; // The .s format to match the instruction with. + dag ResultInst = Result; // The MCInst to generate. + bit EmitAlias = Emit; // Emit the alias instead of what's aliased. + + // Predicates - Predicates that must be true for this to match. + list Predicates = []; +} //===----------------------------------------------------------------------===// // AsmWriter - This class can be implemented by targets that need to customize @@ -552,10 +834,6 @@ class AsmWriter { // name. string AsmWriterClassName = "AsmPrinter"; - // InstFormatName - AsmWriters can specify the name of the format string to - // print instructions with. - string InstFormatName = "AsmString"; - // Variant - AsmWriters can be of multiple different variants. Variants are // used to support targets that need to emit assembly code in ways that are // mostly the same for different targets, but have minor differences in @@ -563,17 +841,22 @@ class AsmWriter { // will specify which alternative to use. For example "{x|y|z}" with Variant // == 1, will expand to "y". int Variant = 0; - - + + // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar // layout, the asmwriter can actually generate output in this columns (in // verbose-asm mode). These two values indicate the width of the first column // (the "opcode" area) and the width to reserve for subsequent operands. When // verbose asm mode is enabled, operands will be indented to respect this. int FirstOperandColumn = -1; - + // OperandSpacing - Space between operand columns. int OperandSpacing = -1; + + // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls + // generation of the printInstruction() method. For MC printers, it takes + // an MCInstr* operand, otherwise it takes a MachineInstr*. + bit isMCAsmWriter = 0; } def DefaultAsmWriter : AsmWriter; @@ -588,6 +871,10 @@ class Target { // AssemblyParsers - The AsmParser instances available for this target. list AssemblyParsers = [DefaultAsmParser]; + /// AssemblyParserVariants - The AsmParserVariant instances available for + /// this target. + list AssemblyParserVariants = [DefaultAsmParserVariant]; + // AssemblyWriters - The AsmWriter instances available for this target. list AssemblyWriters = [DefaultAsmWriter]; } @@ -601,15 +888,15 @@ class SubtargetFeature f> { // appropriate target chip. // string Name = n; - + + // SchedModel - The machine model for scheduling and instruction cost. + // + SchedMachineModel SchedModel = NoSchedModel; + // ProcItin - The scheduling information for the target processor. // ProcessorItineraries ProcItin = pi; - - // Features - list of + + // Features - list of list Features = f; } +// ProcessorModel allows subtargets to specify the more general +// SchedMachineModel instead if a ProcessorItinerary. Subtargets will +// gradually move to this newer form. +class ProcessorModel f> + : Processor { + let SchedModel = m; +} + //===----------------------------------------------------------------------===// // Pull in the common support for calling conventions. //