X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FTarget%2FTargetMachine.h;h=91e4715eea3afe027e5f58de9c2ff1c7ed80fd31;hb=b05bddb4bae4e693225df4c517d9b368d923f1b3;hp=6544ce25f86307a6093413aae160b87d2267c12d;hpb=ab8be96fd30ca9396e6b84fdddf1ac6208984cad;p=oota-llvm.git diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h index 6544ce25f86..91e4715eea3 100644 --- a/include/llvm/Target/TargetMachine.h +++ b/include/llvm/Target/TargetMachine.h @@ -14,6 +14,10 @@ #ifndef LLVM_TARGET_TARGETMACHINE_H #define LLVM_TARGET_TARGETMACHINE_H +#include "llvm/ADT/StringRef.h" +#include "llvm/Pass.h" +#include "llvm/Support/CodeGen.h" +#include "llvm/Target/TargetOptions.h" #include #include @@ -21,65 +25,32 @@ namespace llvm { class InstrItineraryData; class JITCodeEmitter; +class GlobalValue; class MCAsmInfo; +class MCCodeGenInfo; class MCContext; -class Pass; -class PassManager; -class PassManagerBase; class Target; -class TargetData; -class TargetELFWriterInfo; +class DataLayout; +class TargetLibraryInfo; class TargetFrameLowering; class TargetInstrInfo; class TargetIntrinsicInfo; class TargetJITInfo; class TargetLowering; +class TargetPassConfig; class TargetRegisterInfo; class TargetSelectionDAGInfo; -class TargetSubtarget; +class TargetSubtargetInfo; +class ScalarTargetTransformInfo; +class VectorTargetTransformInfo; class formatted_raw_ostream; class raw_ostream; -// Relocation model types. -namespace Reloc { - enum Model { - Default, - Static, - PIC_, // Cannot be named PIC due to collision with -DPIC - DynamicNoPIC - }; -} - -// Code model types. -namespace CodeModel { - enum Model { - Default, - Small, - Kernel, - Medium, - Large - }; -} - -// Code generation optimization level. -namespace CodeGenOpt { - enum Level { - None, // -O0 - Less, // -O1 - Default, // -O2, -Os - Aggressive // -O3 - }; -} - -namespace Sched { - enum Preference { - None, // No preference - Latency, // Scheduling for shortest total latency. - RegPressure, // Scheduling for lowest register pressure. - Hybrid, // Scheduling for both latency and register pressure. - ILP // Scheduling for ILP in low register pressure mode. - }; +// The old pass manager infrastructure is hidden in a legacy namespace now. +namespace legacy { +class PassManagerBase; } +using legacy::PassManagerBase; //===----------------------------------------------------------------------===// /// @@ -88,18 +59,24 @@ namespace Sched { /// through this interface. /// class TargetMachine { - TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT - void operator=(const TargetMachine &); // DO NOT IMPLEMENT + TargetMachine(const TargetMachine &) LLVM_DELETED_FUNCTION; + void operator=(const TargetMachine &) LLVM_DELETED_FUNCTION; protected: // Can only create subclasses. - TargetMachine(const Target &); - - /// getSubtargetImpl - virtual method implemented by subclasses that returns - /// a reference to that target's TargetSubtarget-derived member variable. - virtual const TargetSubtarget *getSubtargetImpl() const { return 0; } + TargetMachine(const Target &T, StringRef TargetTriple, + StringRef CPU, StringRef FS, const TargetOptions &Options); /// TheTarget - The Target that this machine was created for. const Target &TheTarget; + /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target + /// feature strings the TargetMachine instance is created with. + std::string TargetTriple; + std::string TargetCPU; + std::string TargetFS; + + /// CodeGenInfo - Low level target information such as relocation model. + const MCCodeGenInfo *CodeGenInfo; + /// AsmInfo - Contains target specific asm information. /// const MCAsmInfo *AsmInfo; @@ -109,30 +86,47 @@ protected: // Can only create subclasses. unsigned MCSaveTempLabels : 1; unsigned MCUseLoc : 1; unsigned MCUseCFI : 1; + unsigned MCUseDwarfDirectory : 1; public: virtual ~TargetMachine(); const Target &getTarget() const { return TheTarget; } + const StringRef getTargetTriple() const { return TargetTriple; } + const StringRef getTargetCPU() const { return TargetCPU; } + const StringRef getTargetFeatureString() const { return TargetFS; } + + /// getSubtargetImpl - virtual method implemented by subclasses that returns + /// a reference to that target's TargetSubtargetInfo-derived member variable. + virtual const TargetSubtargetInfo *getSubtargetImpl() const { return 0; } + + mutable TargetOptions Options; + + /// \brief Reset the target options based on the function's attributes. + void resetTargetOptions(const MachineFunction *MF) const; + // Interfaces to the major aspects of target machine information: + // // -- Instruction opcode and operand information // -- Pipelines and scheduling information // -- Stack frame information // -- Selection DAG lowering information // + // N.B. These objects may change during compilation. It's not safe to cache + // them between functions. virtual const TargetInstrInfo *getInstrInfo() const { return 0; } virtual const TargetFrameLowering *getFrameLowering() const { return 0; } virtual const TargetLowering *getTargetLowering() const { return 0; } virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; } - virtual const TargetData *getTargetData() const { return 0; } + virtual const DataLayout *getDataLayout() const { return 0; } /// getMCAsmInfo - Return target specific asm information. /// const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; } /// getSubtarget - This method returns a pointer to the specified type of - /// TargetSubtarget. In debug builds, it verifies that the object being + /// TargetSubtargetInfo. In debug builds, it verifies that the object being /// returned is of the correct type. template const STC &getSubtarget() const { return *static_cast(getSubtargetImpl()); @@ -161,11 +155,6 @@ public: return 0; } - /// getELFWriterInfo - If this target supports an ELF writer, return - /// information for it, otherwise return null. - /// - virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; } - /// hasMCRelaxAll - Check whether all machine code instructions should be /// relaxed. bool hasMCRelaxAll() const { return MCRelaxAll; } @@ -200,21 +189,33 @@ public: /// setMCUseCFI - Set whether all we should use dwarf's .cfi_* directives. void setMCUseCFI(bool Value) { MCUseCFI = Value; } + /// hasMCUseDwarfDirectory - Check whether we should use .file directives with + /// explicit directories. + bool hasMCUseDwarfDirectory() const { return MCUseDwarfDirectory; } + + /// setMCUseDwarfDirectory - Set whether all we should use .file directives + /// with explicit directories. + void setMCUseDwarfDirectory(bool Value) { MCUseDwarfDirectory = Value; } + /// getRelocationModel - Returns the code generation relocation model. The /// choices are static, PIC, and dynamic-no-pic, and target default. - static Reloc::Model getRelocationModel(); - - /// setRelocationModel - Sets the code generation relocation model. - /// - static void setRelocationModel(Reloc::Model Model); + Reloc::Model getRelocationModel() const; /// getCodeModel - Returns the code model. The choices are small, kernel, /// medium, large, and target default. - static CodeModel::Model getCodeModel(); + CodeModel::Model getCodeModel() const; - /// setCodeModel - Sets the code model. - /// - static void setCodeModel(CodeModel::Model Model); + /// getTLSModel - Returns the TLS model which should be used for the given + /// global variable. + TLSModel::Model getTLSModel(const GlobalValue *GV) const; + + /// getOptLevel - Returns the optimization level: None, Less, + /// Default, or Aggressive. + CodeGenOpt::Level getOptLevel() const; + + void setFastISel(bool Enable) { Options.EnableFastISel = Enable; } + + bool shouldPrintMachineCode() const { return Options.PrintMachineCode; } /// getAsmVerbosityDefault - Returns the default value of asm verbosity. /// @@ -239,6 +240,9 @@ public: /// sections. static void setFunctionSections(bool); + /// \brief Register analysis passes for this target with a pass manager. + virtual void addAnalysisPasses(PassManagerBase &) {} + /// CodeGenFileType - These enums are meant to be passed into /// addPassesToEmitFile to indicate what type of file to emit, and returned by /// it to indicate what type of file could actually be made. @@ -248,10 +252,6 @@ public: CGFT_Null // Do not emit any output. }; - /// getEnableTailMergeDefault - the default setting for -enable-tail-merge - /// on this target. User flag overrides. - virtual bool getEnableTailMergeDefault() const { return true; } - /// addPassesToEmitFile - Add passes to the specified pass manager to get the /// specified file emitted. Typically this will involve several steps of code /// generation. This method should return true if emission of this file type @@ -259,8 +259,9 @@ public: virtual bool addPassesToEmitFile(PassManagerBase &, formatted_raw_ostream &, CodeGenFileType, - CodeGenOpt::Level, - bool = true) { + bool /*DisableVerify*/ = true, + AnalysisID /*StartAfter*/ = 0, + AnalysisID /*StopAfter*/ = 0) { return true; } @@ -272,8 +273,7 @@ public: /// virtual bool addPassesToEmitMachineCode(PassManagerBase &, JITCodeEmitter &, - CodeGenOpt::Level, - bool = true) { + bool /*DisableVerify*/ = true) { return true; } @@ -285,8 +285,7 @@ public: virtual bool addPassesToEmitMC(PassManagerBase &, MCContext *&, raw_ostream &, - CodeGenOpt::Level, - bool = true) { + bool /*DisableVerify*/ = true) { return true; } }; @@ -295,34 +294,32 @@ public: /// implemented with the LLVM target-independent code generator. /// class LLVMTargetMachine : public TargetMachine { - std::string TargetTriple; - protected: // Can only create subclasses. - LLVMTargetMachine(const Target &T, const std::string &TargetTriple); - -private: - /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for - /// both emitting to assembly files or machine code output. - /// - bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level, - bool DisableVerify, MCContext *&OutCtx); - - virtual void setCodeModelForJIT(); - virtual void setCodeModelForStatic(); + LLVMTargetMachine(const Target &T, StringRef TargetTriple, + StringRef CPU, StringRef FS, TargetOptions Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL); + void initAsmInfo(); public: + /// \brief Register analysis passes for this target with a pass manager. + /// + /// This registers target independent analysis passes. + virtual void addAnalysisPasses(PassManagerBase &PM); - const std::string &getTargetTriple() const { return TargetTriple; } + /// createPassConfig - Create a pass configuration object to be used by + /// addPassToEmitX methods for generating a pipeline of CodeGen passes. + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); /// addPassesToEmitFile - Add passes to the specified pass manager to get the /// specified file emitted. Typically this will involve several steps of code - /// generation. If OptLevel is None, the code generator should emit code as - /// fast as possible, though the generated code may be less efficient. + /// generation. virtual bool addPassesToEmitFile(PassManagerBase &PM, formatted_raw_ostream &Out, CodeGenFileType FileType, - CodeGenOpt::Level, - bool DisableVerify = true); + bool DisableVerify = true, + AnalysisID StartAfter = 0, + AnalysisID StopAfter = 0); /// addPassesToEmitMachineCode - Add passes to the specified pass manager to /// get machine code emitted. This uses a JITCodeEmitter object to handle @@ -332,7 +329,6 @@ public: /// virtual bool addPassesToEmitMachineCode(PassManagerBase &PM, JITCodeEmitter &MCE, - CodeGenOpt::Level, bool DisableVerify = true); /// addPassesToEmitMC - Add passes to the specified pass manager to get @@ -343,65 +339,15 @@ public: virtual bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx, raw_ostream &OS, - CodeGenOpt::Level OptLevel, bool DisableVerify = true); - /// Target-Independent Code Generator Pass Configuration Options. - - /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM - /// passes (which are run just before instruction selector). - virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) { - return true; - } - - /// addInstSelector - This method should install an instruction selector pass, - /// which converts from LLVM code to machine instructions. - virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) { - return true; - } - - /// addPreRegAlloc - This method may be implemented by targets that want to - /// run passes immediately before register allocation. This should return - /// true if -print-machineinstrs should print after these passes. - virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) { - return false; - } - - /// addPostRegAlloc - This method may be implemented by targets that want - /// to run passes after register allocation but before prolog-epilog - /// insertion. This should return true if -print-machineinstrs should print - /// after these passes. - virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) { - return false; - } - - /// addPreSched2 - This method may be implemented by targets that want to - /// run passes after prolog-epilog insertion and before the second instruction - /// scheduling pass. This should return true if -print-machineinstrs should - /// print after these passes. - virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) { - return false; - } - - /// addPreEmitPass - This pass may be implemented by targets that want to run - /// passes immediately before machine code is emitted. This should return - /// true if -print-machineinstrs should print out the code after the passes. - virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) { - return false; - } - - /// addCodeEmitter - This pass should be overridden by the target to add a /// code emitter, if supported. If this is not supported, 'true' should be /// returned. - virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level, + virtual bool addCodeEmitter(PassManagerBase &, JITCodeEmitter &) { return true; } - - /// getEnableTailMergeDefault - the default setting for -enable-tail-merge - /// on this target. User flag overrides. - virtual bool getEnableTailMergeDefault() const { return true; } }; } // End llvm namespace