X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FTarget%2FTargetRegisterInfo.h;h=55eab0bfe406819dcbef7601078e0b90d355b216;hb=1b1f2b2c9499f741e00c3e52f23d9ceb61676627;hp=53fa7ca716743c3d1ef67e9871da65623b2ba17d;hpb=d9524d66cd6a69ded63b29bed5413217444b162a;p=oota-llvm.git diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h index 53fa7ca7167..55eab0bfe40 100644 --- a/include/llvm/Target/TargetRegisterInfo.h +++ b/include/llvm/Target/TargetRegisterInfo.h @@ -18,9 +18,10 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/CodeGen/MachineBasicBlock.h" -#include "llvm/CodeGen/ValueTypes.h" +#include "llvm/CodeGen/MachineValueType.h" #include "llvm/IR/CallingConv.h" #include "llvm/MC/MCRegisterInfo.h" +#include "llvm/Support/CommandLine.h" #include #include @@ -32,6 +33,9 @@ class RegScavenger; template class SmallVectorImpl; class VirtRegMap; class raw_ostream; +class LiveRegMatrix; + +extern cl::opt ForceStackAlign; class TargetRegisterClass { public: @@ -45,6 +49,12 @@ public: const vt_iterator VTs; const uint32_t *SubClassMask; const uint16_t *SuperRegIndices; + const unsigned LaneMask; + /// Classes with a higher priority value are assigned first by register + /// allocators using a greedy heuristic. The value is in the range [0,63]. + const uint8_t AllocationPriority; + /// Whether the class supports two (or more) disjunct subregister indices. + const bool HasDisjunctSubRegs; const sc_iterator SuperClasses; ArrayRef (*OrderFunc)(const MachineFunction&); @@ -52,10 +62,6 @@ public: /// unsigned getID() const { return MC->getID(); } - /// getName() - Return the register class name for debugging. - /// - const char *getName() const { return MC->getName(); } - /// begin/end - Return all of the registers in this class. /// iterator begin() const { return MC->begin(); } @@ -101,9 +107,9 @@ public: /// hasType - return true if this TargetRegisterClass has the ValueType vt. /// - bool hasType(EVT vt) const { + bool hasType(MVT vt) const { for(int i = 0; VTs[i] != MVT::Other; ++i) - if (EVT(VTs[i]) == vt) + if (MVT(VTs[i]) == vt) return true; return false; } @@ -174,7 +180,7 @@ public: /// isASubClass - return true if this TargetRegisterClass is a subset /// class of at least one other TargetRegisterClass. bool isASubClass() const { - return SuperClasses[0] != 0; + return SuperClasses[0] != nullptr; } /// getRawAllocationOrder - Returns the preferred order for allocating @@ -194,6 +200,13 @@ public: ArrayRef getRawAllocationOrder(const MachineFunction &MF) const { return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs()); } + + /// Returns the combination of all lane masks of register in this class. + /// The lane masks of the registers are the combination of all lane masks + /// of their subregisters. + unsigned getLaneMask() const { + return LaneMask; + } }; /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about @@ -306,7 +319,7 @@ public: /// register of the given type, picking the most sub register class of /// the right type that contains this physreg. const TargetRegisterClass * - getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; + getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const; /// getAllocatableClass - Return the maximal subclass of the given register /// class that is alloctable, or NULL. @@ -317,7 +330,7 @@ public: /// indicating if a register is allocatable or not. If a register class is /// specified, returns the subset for the class. BitVector getAllocatableSet(const MachineFunction &MF, - const TargetRegisterClass *RC = NULL) const; + const TargetRegisterClass *RC = nullptr) const; /// getCostPerUse - Return the additional cost of using this register instead /// of other registers in its class. @@ -353,17 +366,30 @@ public: /// /// then: /// - /// getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B) != 0 + /// (getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B)) != 0 /// /// The converse is not necessarily true. If two lane masks have a common /// bit, the corresponding sub-registers may not overlap, but it can be /// assumed that they usually will. + /// SubIdx == 0 is allowed, it has the lane mask ~0u. unsigned getSubRegIndexLaneMask(unsigned SubIdx) const { - // SubIdx == 0 is allowed, it has the lane mask ~0u. assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); return SubRegIndexLaneMasks[SubIdx]; } + /// Returns true if the given lane mask is imprecise. + /// + /// LaneMasks as given by getSubRegIndexLaneMask() have a limited number of + /// bits, so for targets with more than 31 disjunct subregister indices there + /// may be cases where: + /// getSubReg(Reg,A) does not overlap getSubReg(Reg,B) + /// but we still have + /// (getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B)) != 0. + /// This function returns true in those cases. + static bool isImpreciseLaneMask(unsigned LaneMask) { + return LaneMask & 0x80000000u; + } + /// The lane masks returned by getSubRegIndexLaneMask() above can only be /// used to determine if sub-registers overlap - they can't be used to /// determine if a set of sub-registers completely cover another @@ -420,11 +446,11 @@ public: /// order of desired callee-save stack frame offset. The first register is /// closest to the incoming stack pointer if stack grows down, and vice versa. /// - virtual const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF = 0) - const = 0; + virtual const MCPhysReg* + getCalleeSavedRegs(const MachineFunction *MF) const = 0; /// getCallPreservedMask - Return a mask of call-preserved registers for the - /// given calling convention on the current sub-target. The mask should + /// given calling convention on the current function. The mask should /// include all call-preserved aliases. This is used by the register /// allocator to determine which registers can be live across a call. /// @@ -441,17 +467,27 @@ public: /// instructions should use implicit-def operands to indicate call clobbered /// registers. /// - virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const { + virtual const uint32_t *getCallPreservedMask(const MachineFunction &MF, + CallingConv::ID) const { // The default mask clobbers everything. All targets should override. - return 0; + return nullptr; } + /// Return all the call-preserved register masks defined for this target. + virtual ArrayRef getRegMasks() const = 0; + virtual ArrayRef getRegMaskNames() const = 0; + /// getReservedRegs - Returns a bitset indexed by physical register number /// indicating if a register is a special register that has particular uses /// and should be considered unavailable at all times, e.g. SP, RA. This is /// used by register scavenger to determine what registers are free. virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; + /// Prior to adding the live-out mask to a stackmap or patchpoint + /// instruction, provide the target the opportunity to adjust it (mainly to + /// remove pseudo-registers that should be ignored). + virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const { } + /// getMatchingSuperReg - Return a super-register of the specified register /// Reg so its sub-register of index SubIdx is Reg. unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, @@ -506,12 +542,31 @@ public: return composeSubRegIndicesImpl(a, b); } + /// Transforms a LaneMask computed for one subregister to the lanemask that + /// would have been computed when composing the subsubregisters with IdxA + /// first. @sa composeSubRegIndices() + unsigned composeSubRegIndexLaneMask(unsigned IdxA, unsigned LaneMask) const { + if (!IdxA) + return LaneMask; + return composeSubRegIndexLaneMaskImpl(IdxA, LaneMask); + } + + /// Debugging helper: dump register in human readable form to dbgs() stream. + static void dumpReg(unsigned Reg, unsigned SubRegIndex = 0, + const TargetRegisterInfo* TRI = nullptr); + protected: /// Overridden by TableGen in targets that have sub-registers. virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const { llvm_unreachable("Target has no sub-registers"); } + /// Overridden by TableGen in targets that have sub-registers. + virtual unsigned + composeSubRegIndexLaneMaskImpl(unsigned, unsigned) const { + llvm_unreachable("Target has no sub-registers"); + } + public: /// getCommonSuperRegClass - Find a common super-register class if it exists. /// @@ -561,6 +616,11 @@ public: return RegClassBegin[i]; } + /// getRegClassName - Returns the name of the register class. + const char *getRegClassName(const TargetRegisterClass *Class) const { + return MCRegisterInfo::getRegClassName(Class->MC); + } + /// getCommonSubClass - find the largest common subclass of A and B. Return /// NULL if there is no common subclass. const TargetRegisterClass * @@ -589,8 +649,9 @@ public: /// legal to use in the current sub-target and has the same spill size. /// The returned register class can be used to create virtual registers which /// means that all its registers can be copied and spilled. - virtual const TargetRegisterClass* - getLargestLegalSuperClass(const TargetRegisterClass *RC) const { + virtual const TargetRegisterClass * + getLargestLegalSuperClass(const TargetRegisterClass *RC, + const MachineFunction &) const { /// The default implementation is very conservative and doesn't allow the /// register allocator to inflate register classes. return RC; @@ -622,7 +683,8 @@ public: /// Get the register unit pressure limit for this dimension. /// This limit must be adjusted dynamically for reserved registers. - virtual unsigned getRegPressureSetLimit(unsigned Idx) const = 0; + virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, + unsigned Idx) const = 0; /// Get the dimensions of register pressure impacted by this register class. /// Returns a -1 terminated array of pressure set IDs. @@ -651,23 +713,17 @@ public: ArrayRef Order, SmallVectorImpl &Hints, const MachineFunction &MF, - const VirtRegMap *VRM = 0) const; + const VirtRegMap *VRM = nullptr, + const LiveRegMatrix *Matrix = nullptr) + const; - /// avoidWriteAfterWrite - Return true if the register allocator should avoid - /// writing a register from RC in two consecutive instructions. - /// This can avoid pipeline stalls on certain architectures. - /// It does cause increased register pressure, though. - virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { - return false; - } - - /// UpdateRegAllocHint - A callback to allow target a chance to update + /// updateRegAllocHint - A callback to allow target a chance to update /// register allocation hints when a register is "changed" (e.g. coalesced) /// to another register. e.g. On ARM, some virtual registers should target /// register pairs, if one of pair is coalesced to another register, the /// allocation hint of the other half of the pair should be changed to point /// to the new register. - virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, + virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg, MachineFunction &MF) const { // Do nothing. } @@ -683,12 +739,6 @@ public: /// (3) Bottom-up allocation is no longer guaranteed to optimally color. virtual bool reverseLocalAssignment() const { return false; } - /// Allow the target to override register assignment heuristics based on the - /// live range size. If this returns false, then local live ranges are always - /// assigned in order regardless of their size. This is a temporary hook for - /// debugging downstream codegen failures exposed by regalloc. - virtual bool mayOverrideLocalAssignment() const { return true; } - /// Allow the target to override the cost of using a callee-saved register for /// the first time. Default value of 0 means we will use a callee-saved /// register if it is available. @@ -725,7 +775,7 @@ public: /// x86, if the frame register is required, the first fixed stack object is /// reserved as its spill slot. This tells PEI not to create a new stack frame /// object for the given register. It should be called only after - /// processFunctionBeforeCalleeSavedScan(). + /// determineCalleeSaves(). virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const { return false; @@ -737,12 +787,14 @@ public: return false; } + /// canRealignStack - true if the stack can be realigned for the target. + virtual bool canRealignStack(const MachineFunction &MF) const; + /// needsStackRealignment - true if storage within the function requires the /// stack pointer to be aligned more than the normal calling convention calls - /// for. - virtual bool needsStackRealignment(const MachineFunction &MF) const { - return false; - } + /// for. This cannot be overriden by the target, but canRealignStack can be + /// overriden. + bool needsStackRealignment(const MachineFunction &MF) const; /// getFrameIndexInstrOffset - Get the offset from the referenced frame /// index in the instruction, if there is one. @@ -770,14 +822,14 @@ public: /// resolveFrameIndex - Resolve a frame index operand of an instruction /// to reference the indicated base register plus offset instead. - virtual void resolveFrameIndex(MachineBasicBlock::iterator I, - unsigned BaseReg, int64_t Offset) const { + virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, + int64_t Offset) const { llvm_unreachable("resolveFrameIndex does not exist on this target"); } - /// isFrameOffsetLegal - Determine whether a given offset immediate is - /// encodable to resolve a frame index. - virtual bool isFrameOffsetLegal(const MachineInstr *MI, + /// isFrameOffsetLegal - Determine whether a given base register plus offset + /// immediate is encodable to resolve a frame index. + virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const { llvm_unreachable("isFrameOffsetLegal does not exist on this target"); } @@ -805,7 +857,19 @@ public: /// instruction. FIOperandNum is the FI operand number. virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, - RegScavenger *RS = NULL) const = 0; + RegScavenger *RS = nullptr) const = 0; + + //===--------------------------------------------------------------------===// + /// Subtarget Hooks + + /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true. + virtual bool shouldCoalesce(MachineInstr *MI, + const TargetRegisterClass *SrcRC, + unsigned SubReg, + const TargetRegisterClass *DstRC, + unsigned DstSubReg, + const TargetRegisterClass *NewRC) const + { return true; } //===--------------------------------------------------------------------===// /// Debug information queries. @@ -813,12 +877,6 @@ public: /// getFrameRegister - This method should return the register used as a base /// for values allocated in the current stack frame. virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; - - /// getCompactUnwindRegNum - This function maps the register to the number for - /// compact unwind encoding. Return -1 if the register isn't valid. - virtual int getCompactUnwindRegNum(unsigned, bool) const { - return -1; - } }; @@ -874,7 +932,7 @@ public: Mask += RCMaskWords; SubReg = *Idx++; if (!SubReg) - Idx = 0; + Idx = nullptr; } }; @@ -902,7 +960,7 @@ class PrintReg { unsigned Reg; unsigned SubIdx; public: - explicit PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, + explicit PrintReg(unsigned reg, const TargetRegisterInfo *tri = nullptr, unsigned subidx = 0) : TRI(tri), Reg(reg), SubIdx(subidx) {} void print(raw_ostream&) const;