X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FTarget%2FTargetRegisterInfo.h;h=5af90fbf8cddbe990d905768456a43b0f4c726ad;hb=414e5023f8f8b22486313e2867fdb39c7c4f564b;hp=590491aeb800fff2cea132b46a59ab6e01461a9f;hpb=fa4677b483b85217ac216f7e8d401c40cbe348aa;p=oota-llvm.git diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h index 590491aeb80..5af90fbf8cd 100644 --- a/include/llvm/Target/TargetRegisterInfo.h +++ b/include/llvm/Target/TargetRegisterInfo.h @@ -28,6 +28,8 @@ class BitVector; class MachineFunction; class MachineMove; class RegScavenger; +template class SmallVectorImpl; +class raw_ostream; /// TargetRegisterDesc - This record contains all of the information known about /// a particular register. The AliasSet field (if not null) contains a pointer @@ -41,7 +43,6 @@ class RegScavenger; /// of AX. /// struct TargetRegisterDesc { - const char *AsmName; // Assembly language name for the register const char *Name; // Printable name for the reg (for debugging) const unsigned *AliasSet; // Register Alias Set, described above const unsigned *SubRegs; // Sub-register set, described above @@ -53,7 +54,7 @@ public: typedef const unsigned* iterator; typedef const unsigned* const_iterator; - typedef const MVT* vt_iterator; + typedef const EVT* vt_iterator; typedef const TargetRegisterClass* const * sc_iterator; private: unsigned ID; @@ -70,7 +71,7 @@ private: public: TargetRegisterClass(unsigned id, const char *name, - const MVT *vts, + const EVT *vts, const TargetRegisterClass * const *subcs, const TargetRegisterClass * const *supcs, const TargetRegisterClass * const *subregcs, @@ -84,7 +85,7 @@ public: RegSet.insert(*I); } virtual ~TargetRegisterClass() {} // Allow subclasses - + /// getID() - Return the register class ID number. /// unsigned getID() const { return ID; } @@ -110,20 +111,25 @@ public: } /// contains - Return true if the specified register is included in this - /// register class. + /// register class. This does not include virtual registers. bool contains(unsigned Reg) const { return RegSet.count(Reg); } + /// contains - Return true if both registers are in this class. + bool contains(unsigned Reg1, unsigned Reg2) const { + return contains(Reg1) && contains(Reg2); + } + /// hasType - return true if this TargetRegisterClass has the ValueType vt. /// - bool hasType(MVT vt) const { + bool hasType(EVT vt) const { for(int i = 0; VTs[i] != MVT::Other; ++i) if (VTs[i] == vt) return true; return false; } - + /// vt_begin / vt_end - Loop over all of the value types that can be /// represented by values in this register class. vt_iterator vt_begin() const { @@ -152,9 +158,6 @@ public: /// index SubIdx, or NULL if no such class exists. const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const { assert(SubIdx>0 && "Invalid subregister index"); - for (unsigned s = 0; s != SubIdx-1; ++s) - if (!SubRegClasses[s]) - return NULL; return SubRegClasses[SubIdx-1]; } @@ -170,10 +173,10 @@ public: return I; } - /// hasSubClass - return true if the the specified TargetRegisterClass + /// hasSubClass - return true if the specified TargetRegisterClass /// is a proper subset of this TargetRegisterClass. bool hasSubClass(const TargetRegisterClass *cs) const { - for (int i = 0; SubClasses[i] != NULL; ++i) + for (int i = 0; SubClasses[i] != NULL; ++i) if (SubClasses[i] == cs) return true; return false; @@ -184,17 +187,17 @@ public: sc_iterator subclasses_begin() const { return SubClasses; } - + sc_iterator subclasses_end() const { sc_iterator I = SubClasses; while (*I != NULL) ++I; return I; } - + /// hasSuperClass - return true if the specified TargetRegisterClass is a /// proper superset of this TargetRegisterClass. bool hasSuperClass(const TargetRegisterClass *cs) const { - for (int i = 0; SuperClasses[i] != NULL; ++i) + for (int i = 0; SuperClasses[i] != NULL; ++i) if (SuperClasses[i] == cs) return true; return false; @@ -205,7 +208,7 @@ public: sc_iterator superclasses_begin() const { return SuperClasses; } - + sc_iterator superclasses_end() const { sc_iterator I = SuperClasses; while (*I != NULL) ++I; @@ -217,7 +220,7 @@ public: bool isASubClass() const { return SuperClasses[0] != 0; } - + /// allocation_order_begin/end - These methods define a range of registers /// which specify the registers in this class that are valid to register /// allocate, and the preferred order to allocate them in. For example, @@ -225,9 +228,12 @@ public: /// cheaper to allocate caller saved registers. /// /// These methods take a MachineFunction argument, which can be used to tune - /// the allocatable registers based on the characteristics of the function. - /// One simple example is that the frame pointer register can be used if - /// frame-pointer-elimination is performed. + /// the allocatable registers based on the characteristics of the function, + /// subtarget, or other criteria. + /// + /// Register allocators should account for the fact that an allocation + /// order iterator may return a reserved register and always check + /// if the register is allocatable (getAllocatableSet()) before using it. /// /// By default, these methods return all registers in the class. /// @@ -238,8 +244,6 @@ public: return end(); } - - /// getSize - Return the size of the register in bytes, which is also the size /// of a stack slot allocated to hold a spilled copy of this register. unsigned getSize() const { return RegSize; } @@ -265,31 +269,30 @@ class TargetRegisterInfo { protected: const unsigned* SubregHash; const unsigned SubregHashSize; - const unsigned* SuperregHash; - const unsigned SuperregHashSize; const unsigned* AliasesHash; const unsigned AliasesHashSize; public: typedef const TargetRegisterClass * const * regclass_iterator; private: const TargetRegisterDesc *Desc; // Pointer to the descriptor array + const char *const *SubRegIndexNames; // Names of subreg indexes. unsigned NumRegs; // Number of entries in the array regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses int CallFrameSetupOpcode, CallFrameDestroyOpcode; + protected: TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, + const char *const *subregindexnames, int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1, const unsigned* subregs = 0, const unsigned subregsize = 0, - const unsigned* superregs = 0, - const unsigned superregsize = 0, - const unsigned* aliases = 0, - const unsigned aliasessize = 0); + const unsigned* aliases = 0, + const unsigned aliasessize = 0); virtual ~TargetRegisterInfo(); public: @@ -301,8 +304,8 @@ public: /// FirstVirtualRegister - This is the first register number that is /// considered to be a 'virtual' register, which is part of the SSA /// namespace. This must be the same for all targets, which means that each - /// target is limited to 1024 registers. - FirstVirtualRegister = 1024 + /// target is limited to this fixed number of registers. + FirstVirtualRegister = 16384 }; /// isPhysicalRegister - Return true if the specified register number is in @@ -319,16 +322,19 @@ public: return Reg >= FirstVirtualRegister; } - /// getPhysicalRegisterRegClass - Returns the Register Class of a physical - /// register of the given type. If type is MVT::Other, then just return any - /// register class the register belongs to. - virtual const TargetRegisterClass * - getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const; + /// printReg - Print a virtual or physical register on OS. + void printReg(unsigned Reg, raw_ostream &OS) const; + + /// getMinimalPhysRegClass - Returns the Register Class of a physical + /// register of the given type, picking the most sub register class of + /// the right type that contains this physreg. + const TargetRegisterClass * + getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; /// getAllocatableSet - Returns a bitset indexed by register number /// indicating if a register is allocatable or not. If a register class is /// specified, returns the subset for the class. - BitVector getAllocatableSet(MachineFunction &MF, + BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC = NULL) const; const TargetRegisterDesc &operator[](unsigned RegNo) const { @@ -370,12 +376,6 @@ public: return get(RegNo).SuperRegs; } - /// getAsmName - Return the symbolic target-specific name for the - /// specified physical register. - const char *getAsmName(unsigned RegNo) const { - return get(RegNo).AsmName; - } - /// getName - Return the human-readable symbolic target-specific name for the /// specified physical register. const char *getName(unsigned RegNo) const { @@ -388,21 +388,11 @@ public: return NumRegs; } - /// areAliases - Returns true if the two registers alias each other, false - /// otherwise - bool areAliases(unsigned regA, unsigned regB) const { - size_t index = (regA + regB * 37) & (AliasesHashSize-1); - unsigned ProbeAmt = 0; - while (AliasesHash[index*2] != 0 && - AliasesHash[index*2+1] != 0) { - if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB) - return true; - - index = (index + ProbeAmt) & (AliasesHashSize-1); - ProbeAmt += 2; - } - - return false; + /// getSubRegIndexName - Return the human-readable symbolic target-specific + /// name for the specified SubRegIndex. + const char *getSubRegIndexName(unsigned SubIdx) const { + assert(SubIdx && "This is not a subregister index"); + return SubRegIndexNames[SubIdx-1]; } /// regsOverlap - Returns true if the two registers are equal or alias each @@ -413,7 +403,20 @@ public: if (isVirtualRegister(regA) || isVirtualRegister(regB)) return false; - return areAliases(regA, regB); + + // regA and regB are distinct physical registers. Do they alias? + size_t index = (regA + regB * 37) & (AliasesHashSize-1); + unsigned ProbeAmt = 0; + while (AliasesHash[index*2] != 0 && + AliasesHash[index*2+1] != 0) { + if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB) + return true; + + index = (index + ProbeAmt) & (AliasesHashSize-1); + ProbeAmt += 2; + } + + return false; } /// isSubRegister - Returns true if regB is a sub-register of regA. @@ -426,30 +429,18 @@ public: SubregHash[index*2+1] != 0) { if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB) return true; - + index = (index + ProbeAmt) & (SubregHashSize-1); ProbeAmt += 2; } - + return false; } /// isSuperRegister - Returns true if regB is a super-register of regA. /// bool isSuperRegister(unsigned regA, unsigned regB) const { - // SuperregHash is a simple quadratically probed hash table. - size_t index = (regA + regB * 37) & (SuperregHashSize-1); - unsigned ProbeAmt = 2; - while (SuperregHash[index*2] != 0 && - SuperregHash[index*2+1] != 0) { - if (SuperregHash[index*2] == regA && SuperregHash[index*2+1] == regB) - return true; - - index = (index + ProbeAmt) & (SuperregHashSize-1); - ProbeAmt += 2; - } - - return false; + return isSubRegister(regB, regA); } /// getCalleeSavedRegs - Return a null-terminated list of all of the @@ -459,11 +450,6 @@ public: virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) const = 0; - /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred - /// register classes to spill each callee saved register with. The order and - /// length of this list match the getCalleeSaveRegs() list. - virtual const TargetRegisterClass* const *getCalleeSavedRegClasses( - const MachineFunction *MF) const =0; /// getReservedRegs - Returns a bitset indexed by physical register number /// indicating if a register is a special register that has particular uses @@ -476,6 +462,59 @@ public: /// exist. virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; + /// getSubRegIndex - For a given register pair, return the sub-register index + /// if the second register is a sub-register of the first. Return zero + /// otherwise. + virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0; + + /// getMatchingSuperReg - Return a super-register of the specified register + /// Reg so its sub-register of index SubIdx is Reg. + unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, + const TargetRegisterClass *RC) const { + for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs) + if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) + return SR; + return 0; + } + + /// canCombineSubRegIndices - Given a register class and a list of + /// subregister indices, return true if it's possible to combine the + /// subregister indices into one that corresponds to a larger + /// subregister. Return the new subregister index by reference. Note the + /// new index may be zero if the given subregisters can be combined to + /// form the whole register. + virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, + SmallVectorImpl &SubIndices, + unsigned &NewSubIdx) const { + return 0; + } + + /// getMatchingSuperRegClass - Return a subclass of the specified register + /// class A so that each register in it has a sub-register of the + /// specified sub-register index which is in the specified register class B. + virtual const TargetRegisterClass * + getMatchingSuperRegClass(const TargetRegisterClass *A, + const TargetRegisterClass *B, unsigned Idx) const { + return 0; + } + + /// composeSubRegIndices - Return the subregister index you get from composing + /// two subregister indices. + /// + /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) + /// returns c. Note that composeSubRegIndices does not tell you about illegal + /// compositions. If R does not have a subreg a, or R:a does not have a subreg + /// b, composeSubRegIndices doesn't tell you. + /// + /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has + /// ssub_0:S0 - ssub_3:S3 subregs. + /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. + /// + virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const { + // This default implementation is correct for most targets. + return b; + } + //===--------------------------------------------------------------------===// // Register Class Information // @@ -488,17 +527,18 @@ public: unsigned getNumRegClasses() const { return (unsigned)(regclass_end()-regclass_begin()); } - + /// getRegClass - Returns the register class associated with the enumeration /// value. See class TargetOperandInfo. const TargetRegisterClass *getRegClass(unsigned i) const { - assert(i <= getNumRegClasses() && "Register Class ID out of range"); - return i ? RegClassBegin[i - 1] : NULL; + assert(i < getNumRegClasses() && "Register Class ID out of range"); + return RegClassBegin[i]; } /// getPointerRegClass - Returns a TargetRegisterClass used for pointer - /// values. - virtual const TargetRegisterClass *getPointerRegClass() const { + /// values. If a target supports multiple different pointer register classes, + /// kind specifies which one is indicated. + virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const { assert(0 && "Target didn't implement getPointerRegClass!"); return 0; // Must return a value in order to compile with VS 2005 } @@ -511,11 +551,34 @@ public: return NULL; } - /// targetHandlesStackFrameRounding - Returns true if the target is - /// responsible for rounding up the stack frame (probably at emitPrologue - /// time). - virtual bool targetHandlesStackFrameRounding() const { - return false; + /// getAllocationOrder - Returns the register allocation order for a specified + /// register class in the form of a pair of TargetRegisterClass iterators. + virtual std::pair + getAllocationOrder(const TargetRegisterClass *RC, + unsigned HintType, unsigned HintReg, + const MachineFunction &MF) const { + return std::make_pair(RC->allocation_order_begin(MF), + RC->allocation_order_end(MF)); + } + + /// ResolveRegAllocHint - Resolves the specified register allocation hint + /// to a physical register. Returns the physical register if it is successful. + virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, + const MachineFunction &MF) const { + if (Type == 0 && Reg && isPhysicalRegister(Reg)) + return Reg; + return 0; + } + + /// UpdateRegAllocHint - A callback to allow target a chance to update + /// register allocation hints when a register is "changed" (e.g. coalesced) + /// to another register. e.g. On ARM, some virtual registers should target + /// register pairs, if one of pair is coalesced to another register, the + /// allocation hint of the other half of the pair should be changed to point + /// to the new register. + virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, + MachineFunction &MF) const { + // Do nothing. } /// requiresRegisterScavenging - returns true if the target requires (and can @@ -523,28 +586,76 @@ public: virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { return false; } - - /// hasFP - Return true if the specified function should have a dedicated - /// frame pointer register. For most targets this is true only if the function - /// has variable sized allocas or if frame pointer elimination is disabled. - virtual bool hasFP(const MachineFunction &MF) const = 0; - // hasReservedCallFrame - Under normal circumstances, when a frame pointer is - // not required, we reserve argument space for call sites in the function - // immediately on entry to the current function. This eliminates the need for - // add/sub sp brackets around call sites. Returns true if the call frame is - // included as part of the stack frame. - virtual bool hasReservedCallFrame(MachineFunction &MF) const { - return !hasFP(MF); + /// requiresFrameIndexScavenging - returns true if the target requires post + /// PEI scavenging of registers for materializing frame index constants. + virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { + return false; + } + + /// requiresVirtualBaseRegisters - Returns true if the target wants the + /// LocalStackAllocation pass to be run and virtual base registers + /// used for more efficient stack access. + virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { + return false; + } + + /// hasReservedSpillSlot - Return true if target has reserved a spill slot in + /// the stack frame of the given function for the specified register. e.g. On + /// x86, if the frame register is required, the first fixed stack object is + /// reserved as its spill slot. This tells PEI not to create a new stack frame + /// object for the given register. It should be called only after + /// processFunctionBeforeCalleeSavedScan(). + virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, + int &FrameIdx) const { + return false; } - // needsStackRealignment - true if storage within the function requires the - // stack pointer to be aligned more than the normal calling convention calls - // for. + /// needsStackRealignment - true if storage within the function requires the + /// stack pointer to be aligned more than the normal calling convention calls + /// for. virtual bool needsStackRealignment(const MachineFunction &MF) const { return false; } + /// getFrameIndexInstrOffset - Get the offset from the referenced frame + /// index in the instruction, if the is one. + virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, + int Idx) const { + return 0; + } + + /// needsFrameBaseReg - Returns true if the instruction's frame index + /// reference would be better served by a base register other than FP + /// or SP. Used by LocalStackFrameAllocation to determine which frame index + /// references it should create new base registers for. + virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { + return false; + } + + /// materializeFrameBaseRegister - Insert defining instruction(s) for + /// BaseReg to be a pointer to FrameIdx before insertion point I. + virtual void materializeFrameBaseRegister(MachineBasicBlock::iterator I, + unsigned BaseReg, int FrameIdx, + int64_t Offset) const { + assert(0 && "materializeFrameBaseRegister does not exist on this target"); + } + + /// resolveFrameIndex - Resolve a frame index operand of an instruction + /// to reference the indicated base register plus offset instead. + virtual void resolveFrameIndex(MachineBasicBlock::iterator I, + unsigned BaseReg, int64_t Offset) const { + assert(0 && "resolveFrameIndex does not exist on this target"); + } + + /// isFrameOffsetLegal - Determine whether a given offset immediate is + /// encodable to resolve a frame index. + virtual bool isFrameOffsetLegal(const MachineInstr *MI, + int64_t Offset) const { + assert(0 && "isFrameOffsetLegal does not exist on this target"); + return false; // Must return a value in order to compile with VS 2005 + } + /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the /// frame setup/destroy instructions if they exist (-1 otherwise). Some /// targets use pseudo instructions in order to abstract away the difference @@ -571,41 +682,33 @@ public: assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); } - /// processFunctionBeforeCalleeSavedScan - This method is called immediately - /// before PrologEpilogInserter scans the physical registers used to determine - /// what callee saved registers should be spilled. This method is optional. - virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS = NULL) const { - - } - /// processFunctionBeforeFrameFinalized - This method is called immediately - /// before the specified functions frame layout (MF.getFrameInfo()) is - /// finalized. Once the frame is finalized, MO_FrameIndex operands are - /// replaced with direct constants. This method is optional. + /// saveScavengerRegister - Spill the register so it can be used by the + /// register scavenger. Return true if the register was spilled, false + /// otherwise. If this function does not spill the register, the scavenger + /// will instead spill it to the emergency spill slot. /// - virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { + virtual bool saveScavengerRegister(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + MachineBasicBlock::iterator &UseMI, + const TargetRegisterClass *RC, + unsigned Reg) const { + return false; } /// eliminateFrameIndex - This method must be overriden to eliminate abstract /// frame indices from instructions which may use them. The instruction /// referenced by the iterator contains an MO_FrameIndex operand which must be /// eliminated by this method. This method may modify or replace the - /// specified instruction, as long as it keeps the iterator pointing the the + /// specified instruction, as long as it keeps the iterator pointing at the /// finished product. SPAdj is the SP adjustment due to call frame setup /// instruction. virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, RegScavenger *RS=NULL) const = 0; - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into - /// the function. - virtual void emitPrologue(MachineFunction &MF) const = 0; - virtual void emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const = 0; - //===--------------------------------------------------------------------===// /// Debug information queries. - + /// getDwarfRegNum - Map a target register to an equivalent dwarf register /// number. Returns -1 if there is no equivalent value. The second /// parameter allows targets to use different numberings for EH info and @@ -614,29 +717,26 @@ public: /// getFrameRegister - This method should return the register used as a base /// for values allocated in the current stack frame. - virtual unsigned getFrameRegister(MachineFunction &MF) const = 0; + virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; - /// getFrameIndexOffset - Returns the displacement from the frame register to - /// the stack frame of the specified index. - virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const; - /// getRARegister - This method should return the register where the return /// address can be found. virtual unsigned getRARegister() const = 0; - - /// getInitialFrameState - Returns a list of machine moves that are assumed - /// on entry to all functions. Note that LabelID is ignored (assumed to be - /// the beginning of the function.) - virtual void getInitialFrameState(std::vector &Moves) const; }; + // This is useful when building IndexedMaps keyed on virtual registers -struct VirtReg2IndexFunctor : std::unary_function { +struct VirtReg2IndexFunctor : public std::unary_function { unsigned operator()(unsigned Reg) const { return Reg - TargetRegisterInfo::FirstVirtualRegister; } }; +/// getCommonSubClass - find the largest common subclass of A and B. Return NULL +/// if there is no common subclass. +const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A, + const TargetRegisterClass *B); + } // End llvm namespace #endif