X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FTarget%2FTargetSchedule.td;h=0da82fdd8971849fa172824ea9618a3ab382edf7;hb=bf07a512f2fd6bbcd0b217060656e9d12b9da5b0;hp=07eb2ce47c43e723d1dff51a149b48e6c6cba8cf;hpb=a2ed0e8e8b89f7e8374ed8b915ee9d4aadf3659a;p=oota-llvm.git

diff --git a/include/llvm/Target/TargetSchedule.td b/include/llvm/Target/TargetSchedule.td
index 07eb2ce47c4..0da82fdd897 100644
--- a/include/llvm/Target/TargetSchedule.td
+++ b/include/llvm/Target/TargetSchedule.td
@@ -55,6 +55,15 @@ include "llvm/Target/TargetItinerary.td"
 
 class Instruction; // Forward def
 
+// DAG operator that interprets the DAG args as Instruction defs.
+def instrs;
+
+// DAG operator that interprets each DAG arg as a regex pattern for
+// matching Instruction opcode names.
+// The regex must match the beginning of the opcode (as in Python re.match).
+// To avoid matching prefixes, append '$' to the pattern.
+def instregex;
+
 // Define the SchedMachineModel and provide basic properties for
 // coarse grained instruction cost model. Default values for the
 // properties are defined in MCSchedModel. A value of "-1" in the
@@ -101,6 +110,10 @@ class ProcResourceKind;
 // cycle that the instruction issues in-order, forcing an interlock
 // with subsequent instructions that require the same resource until
 // the number of ResourceCyles specified in WriteRes expire.
+//
+// SchedModel ties these units to a processor for any stand-alone defs
+// of this class. Instances of subclass ProcResource will be automatically
+// attached to a processor, so SchedModel is not needed.
 class ProcResourceUnits<ProcResourceKind kind, int num> {
   ProcResourceKind Kind = kind;
   int NumUnits = num;
@@ -152,12 +165,17 @@ class SchedRead  : SchedReadWrite;
 // If the final write in this sequence is a SchedWriteVariant marked
 // Variadic, then the list of prior writes are distributed across all
 // operands after resolving the predicate for the final write.
+//
+// SchedModel silences warnings but is ignored.
 class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite {
   list<SchedWrite> Writes = writes;
   int Repeat = rep;
+  SchedMachineModel SchedModel = ?;
 }
 
 // Define values common to WriteRes and SchedWriteRes.
+//
+// SchedModel ties these resources to a processor.
 class ProcWriteResources<list<ProcResourceKind> resources> {
   list<ProcResourceKind> ProcResources = resources;
   list<int> ResourceCycles = [];
@@ -217,12 +235,15 @@ class SchedWriteRes<list<ProcResourceKind> resources> : SchedWrite,
   ProcWriteResources<resources>;
 
 // Define values common to ReadAdvance and SchedReadAdvance.
+//
+// SchedModel ties these resources to a processor.
 class ProcReadAdvance<int cycles, list<SchedWrite> writes = []> {
   int Cycles = cycles;
   list<SchedWrite> ValidWrites = writes;
   // Allow a processor to mark some scheduling classes as unsupported
   // for stronger verification.
   bit Unsupported = 0;
+  SchedMachineModel SchedModel = ?;
 }
 
 // A processor may define a ReadAdvance associated with a SchedRead
@@ -237,7 +258,6 @@ class ProcReadAdvance<int cycles, list<SchedWrite> writes = []> {
 // to issue earlier relative to the writer.
 class ReadAdvance<SchedRead read, int cycles, list<SchedWrite> writes = []>
   : ProcReadAdvance<cycles, writes> {
-  SchedMachineModel SchedModel = ?;
   SchedRead ReadType = read;
 }
 
@@ -261,6 +281,8 @@ class PredicateProlog<code c> {
 // particular MachineInstr. The code snippet is used as an
 // if-statement's expression. Available variables are MI, SchedModel,
 // and anything defined in a PredicateProlog.
+//
+// SchedModel silences warnings but is ignored.
 class SchedPredicate<code pred> {
   SchedMachineModel SchedModel = ?;
   code Predicate = pred;
@@ -281,6 +303,7 @@ class SchedVar<SchedPredicate pred, list<SchedReadWrite> selected> {
   list<SchedReadWrite> Selected = selected;
 }
 
+// SchedModel silences warnings but is ignored.
 class SchedVariant<list<SchedVar> variants> {
   list<SchedVar> Variants = variants;
   bit Variadic = 0;
@@ -309,17 +332,34 @@ class SchedReadVariant<list<SchedVar> variants> : SchedRead,
 
 // Map a set of opcodes to a list of SchedReadWrite types. This allows
 // the subtarget to easily override specific operations.
-class InstRW<list<SchedReadWrite> rw, list<Instruction> instrs> {
+//
+// SchedModel ties this opcode mapping to a processor.
+class InstRW<list<SchedReadWrite> rw, dag instrlist> {
   list<SchedReadWrite> OperandReadWrites = rw;
-  list<Instruction> Instrs = instrs;
+  dag Instrs = instrlist;
   SchedMachineModel SchedModel = ?;
 }
 
 // Map a set of itinerary classes to SchedReadWrite resources. This is
 // used to bootstrap a target (e.g. ARM) when itineraries already
 // exist and changing InstrInfo is undesirable.
+//
+// SchedModel ties this ItineraryClass mapping to a processor.
 class ItinRW<list<SchedReadWrite> rw, list<InstrItinClass> iic> {
   list<InstrItinClass> MatchedItinClasses = iic;
   list<SchedReadWrite> OperandReadWrites = rw;
   SchedMachineModel SchedModel = ?;
 }
+
+// Alias a target-defined SchedReadWrite to a processor specific
+// SchedReadWrite. This allows a subtarget to easily map a
+// SchedReadWrite type onto a WriteSequence, SchedWriteVariant, or
+// SchedReadVariant.
+//
+// SchedModel will usually be provided by surrounding let statement
+// and ties this SchedAlias mapping to a processor.
+class SchedAlias<SchedReadWrite match, SchedReadWrite alias> {
+  SchedReadWrite MatchRW = match;
+  SchedReadWrite AliasRW = alias;
+  SchedMachineModel SchedModel = ?;
+}