X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FTarget%2FTargetSchedule.td;h=89db37ca859b600963f6c398f85353f19b94d895;hb=320efb05a1e7516268e711901ca9454bb4d94172;hp=cf3d2505906cc5408f2706268b60f4a7a73b96cc;hpb=92649883119aaa8edd9ccf612eaaff5ccc8fcc77;p=oota-llvm.git diff --git a/include/llvm/Target/TargetSchedule.td b/include/llvm/Target/TargetSchedule.td index cf3d2505906..89db37ca859 100644 --- a/include/llvm/Target/TargetSchedule.td +++ b/include/llvm/Target/TargetSchedule.td @@ -55,6 +55,15 @@ include "llvm/Target/TargetItinerary.td" class Instruction; // Forward def +// DAG operator that interprets the DAG args as Instruction defs. +def instrs; + +// DAG operator that interprets each DAG arg as a regex pattern for +// matching Instruction opcode names. +// The regex must match the beginning of the opcode (as in Python re.match). +// To avoid matching prefixes, append '$' to the pattern. +def instregex; + // Define the SchedMachineModel and provide basic properties for // coarse grained instruction cost model. Default values for the // properties are defined in MCSchedModel. A value of "-1" in the @@ -63,10 +72,15 @@ class Instruction; // Forward def // // Target hooks allow subtargets to associate LoadLatency and // HighLatency with groups of opcodes. +// +// See MCSchedule.h for detailed comments. class SchedMachineModel { int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle. - int MinLatency = -1; // Determines which instrucions are allowed in a group. + int MinLatency = -1; // Determines which instructions are allowed in a group. // (-1) inorder (0) ooo, (1): inorder +var latencies. + int MicroOpBufferSize = -1; // Max micro-ops that can be buffered. + int LoopMicroOpBufferSize = -1; // Max micro-ops that can be buffered for + // optimized loop dispatch/execution. int LoadLatency = -1; // Cycles for loads to access the cache. int HighLatency = -1; // Approximation of cycles for "high latency" ops. int MispredictPenalty = -1; // Extra cycles for a mispredicted branch. @@ -74,6 +88,17 @@ class SchedMachineModel { // Per-cycle resources tables. ProcessorItineraries Itineraries = NoItineraries; + bit PostRAScheduler = 0; // Enable Post RegAlloc Scheduler pass. + + // Subtargets that define a model for only a subset of instructions + // that have a scheduling class (itinerary class or SchedRW list) + // and may actually be generated for that subtarget must clear this + // bit. Otherwise, the scheduler considers an unmodelled opcode to + // be an error. This should only be set during initial bringup, + // or there will be no way to catch simple errors in the model + // resulting from changes to the instruction definitions. + bit CompleteModel = 1; + bit NoModel = 0; // Special tag to indicate missing machine model. } @@ -93,14 +118,46 @@ class ProcResourceKind; // resources implies using one of the super resoruces. // // ProcResourceUnits normally model a few buffered resources within an -// out-of-order engine that the compiler attempts to conserve. -// Buffered resources may be held for multiple clock cycles, but the -// scheduler does not pin them to a particular clock cycle relative to -// instruction dispatch. Setting Buffered=0 changes this to an -// in-order resource. In this case, the scheduler counts down from the -// cycle that the instruction issues in-order, forcing an interlock -// with subsequent instructions that require the same resource until -// the number of ResourceCyles specified in WriteRes expire. +// out-of-order engine. Buffered resources may be held for multiple +// clock cycles, but the scheduler does not pin them to a particular +// clock cycle relative to instruction dispatch. Setting BufferSize=0 +// changes this to an in-order issue/dispatch resource. In this case, +// the scheduler counts down from the cycle that the instruction +// issues in-order, forcing a stall whenever a subsequent instruction +// requires the same resource until the number of ResourceCyles +// specified in WriteRes expire. Setting BufferSize=1 changes this to +// an in-order latency resource. In this case, the scheduler models +// producer/consumer stalls between instructions that use the +// resource. +// +// Examples (all assume an out-of-order engine): +// +// Use BufferSize = -1 for "issue ports" fed by a unified reservation +// station. Here the size of the reservation station is modeled by +// MicroOpBufferSize, which should be the minimum size of either the +// register rename pool, unified reservation station, or reorder +// buffer. +// +// Use BufferSize = 0 for resources that force "dispatch/issue +// groups". (Different processors define dispath/issue +// differently. Here we refer to stage between decoding into micro-ops +// and moving them into a reservation station.) Normally NumMicroOps +// is sufficient to limit dispatch/issue groups. However, some +// processors can form groups of with only certain combinitions of +// instruction types. e.g. POWER7. +// +// Use BufferSize = 1 for in-order execution units. This is used for +// an in-order pipeline within an out-of-order core where scheduling +// dependent operations back-to-back is guaranteed to cause a +// bubble. e.g. Cortex-a9 floating-point. +// +// Use BufferSize > 1 for out-of-order executions units with a +// separate reservation station. This simply models the size of the +// reservation station. +// +// To model both dispatch/issue groups and in-order execution units, +// create two types of units, one with BufferSize=0 and one with +// BufferSize=1. // // SchedModel ties these units to a processor for any stand-alone defs // of this class. Instances of subclass ProcResource will be automatically @@ -109,7 +166,7 @@ class ProcResourceUnits { ProcResourceKind Kind = kind; int NumUnits = num; ProcResourceKind Super = ?; - bit Buffered = 1; + int BufferSize = -1; SchedMachineModel SchedModel = ?; } @@ -123,6 +180,12 @@ def EponymousProcResourceKind : ProcResourceKind; class ProcResource : ProcResourceKind, ProcResourceUnits; +class ProcResGroup resources> : ProcResourceKind { + list Resources = resources; + SchedMachineModel SchedModel = ?; + int BufferSize = -1; +} + // A target architecture may define SchedReadWrite types and associate // them with instruction operands. class SchedReadWrite; @@ -325,9 +388,9 @@ class SchedReadVariant variants> : SchedRead, // the subtarget to easily override specific operations. // // SchedModel ties this opcode mapping to a processor. -class InstRW rw, list instrs> { +class InstRW rw, dag instrlist> { list OperandReadWrites = rw; - list Instrs = instrs; + dag Instrs = instrlist; SchedMachineModel SchedModel = ?; }